Senior CAD Verification Engineer II – PERC/DRC Flows

Microchip; Town of Montana (WI); On-site; USD 120,000 - 190,000; Full time

Job summary

Microchip Technology Inc. is seeking a seasoned physical verification engineer to support back-end design verification for multiple technology nodes. The role emphasizes developing and maintaining PV flows, regression tests, and toolbox automation.

The ideal candidate has deep Calibre/Pegasus/PERC experience, strong scripting skills in Tcl/Tk and Python, and proven ability to debug PV issues across EDA tools. Occasional travel and collaboration with global teams are expected.

Qualifications

• Bachelors in Electrical Engineering or related field with 7.5 to 10 years experience developing and supporting physical verification activities.
• In depth knowledge of Calibre DesignRev scripting.
• Fluent with SVRF and TVF.
• Accomplished at debugging PV issues with RVE, Vue or other EDA visualizer.
• Familiar with customizing Calibre Interactive.
• Skilled with Tcl/Tk, Perl, Python, and other programming languages, inside and outside of EDA tools.
• Solid knowledge of layout rules and concepts, device identification concepts, and foundry rules.
• Strong knowledge of Design for Manufacturing solutions affecting quality, reliability, and yield of designs.
• Prefer extensive knowledge of Calibre/Pegasus/Hercules syntax and semantics, or similar layout verification tool.
• Strong knowledge of Cadence Virtuoso and/or CalibreDRV.

Responsibilities

• Develop physical verification regression test cases to QA physical verification decks
• Support Layout and Design engineers with physical verification activities using verification tools such as Siemens Calibre, Cadence Pegasus, or Synopsys Hercules
• Utilize Knowledge of advanced EDA methods to support ESD, ERC, Voltage-Aware DRC, via doubling methodologies, etc.
• Work with Technology Development and Device Engineering to develop DRC rules, additional devices, and design for manufacturability checks
• Develop rule decks as needed to support flow
• Verify and enhance foundry rule decks
• Support remote sites worldwide with layout verification activities
• Support debug of physical verification issues
• Work as a member of team to develop flows to improve quality and reliability of devices
• The tasks this candidate will be assigned depends on their experience. There are several areas in which we are shorthanded. Potential task assignments would include:
• Building of regression test cases for several PDKs of various process technologies
• Supporting 4nm to 600nm PDKs from TSMC, Global Foundries, Vanguard, Dongbu, Magnachip, etc.
• Calibre/Pegasus PERC - several PDKs still require PERC setup.

Skills

Calibre

PERC

SVRF

TVF

Tcl/Tk

Python

Debug PV

Education

Bachelors in Electrical Engineering

Masters in Electrical Engineering (preferred)

Tools

Cadence Pegasus

CalibreDRV

Hercules

Cadence Virtuoso

Job description

Microchip Technology Inc. is seeking a seasoned physical verification engineer to support back-end design verification for multiple technology nodes. The role emphasizes developing and maintaining PV flows, regression tests, and toolbox automation.

The ideal candidate has deep Calibre/Pegasus/PERC experience, strong scripting skills in Tcl/Tk and Python, and proven ability to debug PV issues across EDA tools. Occasional travel and collaboration with global teams are expected.