Senior CAD Engineer - Physical Verification

Micron; Boise (ID); On-site; USD 110,000 - 160,000; Full time

Job summary

Micron Technology in Boise, Idaho is seeking a senior verification engineer to develop and maintain physical verification tools for memory products.

You will collaborate across process, design, layout, and modeling teams to define sign-off strategies, automate verification, and drive continuous improvements in DRC/LVS workflows.

Strong background in CMOS/VLSI and experience with Calibre and SVRF are highly valued, as is the ability to communicate across global teams.

Qualifications

• Bachelor's or Master's degree in Electrical/Computer Engineering or CS.
• 5+ years in CAD/EDA or semiconductor design.
• Experience with DRC and LVS, IC layout and process rules.
• Ability to interpret design-rule requirements and resolve issues.
• Proficiency in Python and at least one other language; Linux/Unix & shell scripting.

Responsibilities

• Develop and maintain verification tools, flows, and methodologies for DRAM, HBM, NAND.
• Translate process rules into verification checks and define test cases.
• Collaborate with process, design, layout, modeling, and verification teams on signoffs.
• Guide teams on verification methods, waivers, debugging, and production support.
• Automate verification setup, execution, and reporting, including AI-assisted analysis.

Skills

Python

C/C++

SKILL

Tcl

Perl

Linux/Unix

Shell scripting

CMOS fundamentals

VLSI fundamentals

CAD/EDA

Semiconductor design

Education

Electrical/Computer Engineering or CS degree

Tools

Cadence Virtuoso

Calibre DRC/LVS

SVRF

nmDRC

nmLVS

RVE

Job description

Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities

• Develop and maintain physical verification tools, flows, and methodologies for DRAM, HBM, NAND, and emerging memory products.
• Develop, debug, qualify, and release Siemens Calibre design rule checking (DRC) and layout versus schematic (LVS) rule decks using Standard Verification Rule Format (SVRF).
• Translate process design rules into verification checks, and define the test cases, coverage criteria, and regression methods that qualify them.
• Partner with process, design, layout, modeling, and verification teams to define signoff strategies and resolve verification issues.
• Guide design teams on verification methodologies, waivers, and debugging, and provide training, documentation, and production support.
• Evaluate EDA technologies that improve verification quality, performance, and capacity.
• Automate verification setup, execution, and reporting, including AI-assisted analysis and debugging.
• Lead technical projects and contribute to the physical verification roadmap.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science, or equivalent.
• 5+ years of industry experience in CAD, EDA, or semiconductor design.
• Experience with DRC and LVS physical verification , IC layout, and process design rules.
• Ability to interpret design-rule requirements and resolve complex verification issues in production flows.
• Proficiency in Python and at least one additional language, such as SKILL, Tcl, Perl, C, or C++, plus Linux/Unix and shell scripting.
• Solid CMOS and VLSI fundamentals , with clear communication and practical debugging skills across global teams.

Preferred Qualifications

• Experience developing and qualifying Calibre DRC and LVS rule decks in SVRF, using nmDRC, nmLVS, and Results Viewing Environment (RVE).
• Knowledge of layout-dependent effects and electrical rule checking (ERC), programmable ERC (PERC), antenna, and density checks.
• Experience optimizing rule‑deck coverage, runtime, and memory use.
• Experience with Cadence Virtuoso, SKILL, or Cadence physical verification tools.
• Experience applying AI/ML, large language models, or agentic AI to engineering workflows.
• Experience with source control, automated testing, and release management.
• Knowledge of DRAM, HBM, NAND, or emerging memory development.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time‑off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.