Senior ASIC Verification Engineer — Equity Eligible

NVIDIA AI; Santa Clara (CA); On-site; USD 136,000 - 264,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking ASIC Verification Engineers to verify GPUs, focusing on unit level verification of process scheduling and system interface hardware. You will work across software, architecture, design, and methodology teams to drive verification strategy and post-silicon activities.

Ideal candidates have strong SystemVerilog skills, test planning, coverage closure, and an understanding of computer architecture.

Qualifications

• BS or MS in electrical engineering or computer engineering (or equivalent experience).
• 5+ years of verification experience.
• Exposure to Computer Architecture, ASIC design and verification methodology.
• Strong SystemVerilog, test planning, coverage closure, and test bench design.
• Understanding of object oriented programming concepts.
• Strong communication skills.
• Ability and desire to work as a great teammate.
• Good debugging and problem solving skills.

Responsibilities

• Work on a unit level testbench with directed and random tests.
• Partner with RTL and architecture teams to refine microarchitecture plans.
• Architect and plan verification strategy for sub-system features.
• Support post-silicon validation activities.
• Leverage AI to accelerate testbench development and debugging.

Skills

SystemVerilog

Test planning

Test bench design

Coverage closure

Object oriented programming

Communication skills

Teamwork

Debugging

Problem solving

Education

BS or MS in electrical engineering or computer engineering (or equivalent experience)

Tools

UVM

SFV

SystemVerilog checkers

Scoreboards

Job description

NVIDIA is seeking ASIC Verification Engineers to verify GPUs, focusing on unit level verification of process scheduling and system interface hardware. You will work across software, architecture, design, and methodology teams to drive verification strategy and post-silicon activities.

Ideal candidates have strong SystemVerilog skills, test planning, coverage closure, and an understanding of computer architecture.