Senior ASIC Program Lead for Global SoC Development

AMD; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Job summary

AMD is seeking a Chief Engineer to lead the AECG ASIC program from customer engagement through mass production in San Jose or Austin. You will provide cross-functional leadership across architecture, design, verification, and production ramp to ensure schedule, cost and quality targets are met.

This strategic role builds high-performing teams and drives end-to-end SoC development for next-gen computing experiences.

Qualifications

• BS or MS in Electrical Engineering or Computer Science; ~15 years ASIC leadership experience.
• Experience leading multi-site, multi-disciplinary SOC programs.
• Strong understanding of silicon engineering processes from concept to tape-out.
• Ability to develop end-to-end SoC/Platform plans and communicate findings to senior management.
• Excellent communication and leadership of world-class engineers.

Responsibilities

• Lead scoping and cross-functional leadership for AECG ASIC product development from customer engagement through mass production.
• Direct and matrix-manage program management, design, verification, technology, system, product, software and quality teams.
• Report to AECG engineering and business leadership; plan, status, decisions, debug and customer issues.
• Ensure products meet specification across design and development teams; manage risk and execution.
• Drive PPA commitments and ensure execution to meet objectives.

Skills

SoC leadership

Program management

Architectural design

Design verification

Power/Performance optimization

Executive communication

Cross-site leadership

Silicon engineering process

Education

Bachelor's or Master's in Electrical Engineering or Computer Science

Job description

AMD is seeking a Chief Engineer to lead the AECG ASIC program from customer engagement through mass production in San Jose or Austin. You will provide cross-functional leadership across architecture, design, verification, and production ramp to ensure schedule, cost and quality targets are met.

This strategic role builds high-performing teams and drives end-to-end SoC development for next-gen computing experiences.