Senior ASIC Physical Design Engineer, Netlisting

NVIDIA; United States; Hybrid; USD 150,000 - 230,000; Full time

Job summary

NVIDIA is seeking a Senior ASIC Physical Design Engineer, Netlisting, to lead high-frequency, low-power block- and full-chip design efforts. You will own netlist-related checks, timing convergence, and ECO execution across complex SoCs.

The role requires RTL-to-tapeout expertise, strong EDA tool knowledge, and scripting skills to optimize hardware architectures and timing closures for NVIDIA's cutting-edge devices.

Qualifications

• BS or MS in Electrical or Computer Engineering with related experience.
• Experience with logic equivalence checking and timing closure.
• Deep understanding of hardware architecture and RTL/logic design for timing closure.
• Experience in clock-domain-crossing checking and MTBF analysis.
• Background with logic synthesis at block or full-chip level.
• Strong experience in full-chip STA and timing convergence.
• Expertise with industry standard EDA tools in related fields.
• Proficiency in scripting languages like Perl, TCL, Python.

Responsibilities

• Drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block, cluster, or full-chip level with focus on netlist-related aspects.
• Drive timing convergence, timing constraints generation and management, and ECO generation and implementation.
• Collaborate with design teams to meet timing, power, and area targets while maintaining quality of netlists.

Skills

Timing closure

Clock-domain crossing

RTL-to-tapeout

EDA tools

Scripting languages

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

RTL-to-tapeout tools

In-house tools

Perl/TCL/Python

Job description

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a \"learning machine\" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.

We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a \"learning machine\" that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human inventiveness and intelligence.

What you'll be doing:

• You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.


• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years' experience or MS (or equivalent experience) with 3+ years' experience.


• Expertise in logic equivalence checking/FV required from RTL to tapeout with industry-standard tools. Deep understanding of hardware architecture and hands-on skills


• in RTL/logic design for timing closure.


• Experience in clock-domain-crossing checking, MTBF analysis, either with industry-standard tools or in-house tools.


• Background with logic synthesis at either block or full-chip level, at project execution and/or flow development.


• Strong experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.


• Expertise and in-depth knowledge of industry standard EDA tools in related fields.


• Proficiency in programming and scripting languages, such as, Perl, TCL, Make, Python, etc.

Ways to stand out from the crowd:

• Experience in logic synthesis and equivalence checking/FV. Familiarity with industry tools and flow.


• Strong hands-on debugging capability and problem-solving skills.


• Background in DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.


• Candidates who demonstrate experience or a strong drive to improve workflows and productivity through effective AI utilization will stand out.

NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us.

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.

The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits .

Applications for this job will be accepted at least until September 21, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.