Senior ASIC Design Engineer — RTL, Timing & Tapeouts

Upscale AI, Inc.; Northern (KY); Hybrid; USD 250,000 - 265,000; Full time

Job summary

Upscale, Inc. is building high-performance AI infrastructure with a strong focus on silicon, systems, and networking. We seek a senior ASIC design engineer to define micro-architecture and deliver RTL that meets power, performance, and area targets.

You will collaborate with architecture, verification, physical design, and DFT teams to drive design fixes and ensure robust tapeouts in a fast-paced startup environment. The role requires strong SysVerilog expertise and 5+ years in ASIC logic design.

Qualifications

• BE or MS in EE, CE, CS.
• 5+ years of engineering experience in logic design for ASICs.
• Experience with SystemVerilog for logic design.
• Understanding of logic design fundamentals, clock domain crossing, synthesis and timing closure.
• Strong communication and teamwork in a fast-paced startup.

Responsibilities

• Define and document micro-architecture for next-gen ASIC designs.
• Logic design/RTL entry meeting power, performance, area targets.
• Collaborate with verification and emulation to confirm test plans meet architecture goals.
• Work with physical design on timing closure and area optimization.
• Coordinate with test, and drive DFT integration.
• Communicate effectively and collaborate with cross-functional teams.

Skills

SystemVerilog

Logic design

Timing closure

Clock domain crossing

Communication

Startup experience

Education

BE/MS in EE/CE/CS

Tools

LINT

CDC

RDC

Python

Job description

Upscale, Inc. is building high-performance AI infrastructure with a strong focus on silicon, systems, and networking. We seek a senior ASIC design engineer to define micro-architecture and deliver RTL that meets power, performance, and area targets.

You will collaborate with architecture, verification, physical design, and DFT teams to drive design fixes and ensure robust tapeouts in a fast-paced startup environment. The role requires strong SysVerilog expertise and 5+ years in ASIC logic design.