Senior ASIC Design Engineer-Emulation(HAPS Engineer) 8+ years

SAIS; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

A leading company is seeking a Senior ASIC Design Engineer specializing in HAPS-based emulation. The role involves mapping SoC designs to FPGA platforms, creating design partitions, and collaborating across teams to ensure performance goals are met. Ideal candidates have extensive experience in FPGA prototyping, debugging, and scripting. Join us to shape the future of silicon technology!

Qualifications

• 10+ years experience with Bachelor's or 8+ years with Master's.
• Strong knowledge of CDC, RDC, and RTL (Verilog/System Verilog).
• Hands-on experience with Networking SoCs, PCIE, DDR, Ethernet.

Responsibilities

• Map multi-million gate SoC designs to FPGA platforms.
• Create design partitions and develop simulation testbenches.
• Collaborate across teams to meet functional and performance goals.

Skills

FPGA prototyping

HAPS-based emulation

Debugging

Root cause analysis

Scripting

Education

Bachelor’s in Electrical/Computer Engineering

Master’s in Electrical/Computer Engineering

Tools

Cadence Z2

ZeBu

Job description

Senior ASIC Design Engineer - Emulation (HAPS Engineer) 8+ years

Are you an expert in FPGA prototyping and HAPS-based emulation with a solid ASIC design background? Join us in enabling the next generation of SoCs by working hands-on with cutting-edge prototyping platforms!

As a Senior ASIC Design Engineer – Emulation (HAPS Engineer), you'll:

1. Map multi-million gate SoC designs to FPGA platforms like HAPS.
2. Create design partitions, build FPGAs, and develop simulation testbenches.
3. Set up prototyping systems in the lab and define prototyping methodologies.
4. Collaborate across teams (Design, Software, Verification) to meet functional and performance goals.
5. Optional: Get involved in RTL design and IP integration.

Qualifications:

• Bachelor’s (10+ yrs exp) or Master’s (8+ yrs exp) in Electrical/Computer Engineering.
• Strong knowledge of CDC, RDC, and RTL (Verilog/System Verilog).
• Deep understanding of HAPS prototyping flow and bring-up troubleshooting.
• Proven experience in debugging and root cause analysis across FPGA development stages.
• Experience with Networking SoCs, PCIE, DDR, Ethernet, and ARM/RISCV CPUs.
• Hands-on with platforms like Cadence Z2, ZeBu.
• Advanced scripting skills in TCL, Python, or Perl.

Interested or know someone perfect for the role? Send your resume to [e-mail]

Let’s build the future of silicon together!