Senior Analog Layout Engineer

Cisco Systems; Carlsbad (CA); On-site; USD 149,000 - 218,000; Full time

Job summary

Cisco Systems seeks a Senior Analog/Layout Engineer to architect physical blueprints for high-speed optical interconnects on the Silicon One platform. You will own block-to-top integration for 100G–400G lambda architectures, guiding from floorplanning through post-layout signoff and silicon bring-up.

You will collaborate with CAD, circuit, and packaging teams to optimize parasitics, thermal behavior, and signal integrity while mentoring junior engineers and shaping layout methodologies in a

Qualifications

• Bachelor's degree plus 7 years of related experience, or Master's with 4 years, or PhD with 1 year
• Experience supporting block-level layout through tapeout
• Experience in physical verification and custom layout design for FINFET 7nm/5nm/3nm
• Experience with Cadence Virtuoso or similar custom layout tools
• Experience with ASIC/SoC tapeout processes and scripting (Python, Perl, TCL) for layout automation

Responsibilities

• Power Next-Gen Optics: build and optimize analog/mixed-signal layouts for 100G–400G/lambda optical solutions
• Own the Silicon Lifecycle: drive full-flow from concept to sign-off, tapeout and bring-up
• Solve High-Speed Challenges: manage parasitics, SI and thermal tradeoffs with CAD teams
• Set the Standard: shape design methodologies and mentor rising engineers

Skills

Analog layout

Physical verification

Tapeout experience

Scripting (Python/Perl/TCL)

Education

Bachelor's degree in related field

Master's degree (advantage)

PhD (advantage)

Tools

Cadence Virtuoso

Calibre

Job description

The application window is expected to close on: 01/18/2027

Meet the Team

The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

Your Impact

As a Senior Analog Layout Engineer on the Silicon One Optics team, you won’t just be drawing polygons—you’ll be architecting the physical blueprint for the world’s fastest optical interconnects. You will own block-to-top integration for next-gen 100G, 200G, and 400G per lambda architectures, pushing silicon past standard limits. From initial floorplanning to sign-off tapeout and silicon bring-up, your physical design decisions will directly power the future of global AI and data center infrastructure.

• Power Next-Gen Optics: Directly build and optimize complex analog and mixed-signal layouts for groundbreaking 100G–400G/lambda optical solutions.
• Own the Silicon Lifecycle: Drive full-flow execution from concept and floorplanning through post-layout extraction, sign-off, tapeout, and post-silicon bring-up.
• Solve High-Speed Challenges: Master complex parasitic, signal integrity, and thermal tradeoffs alongside world-class circuit design, packaging, and CAD teams.
• Set the Standard: Shape design methodologies, mentor rising engineering talent, and raise the bar for physical execution across the group.

Minimum Qualifications

• Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 1 year of related experience
• Prior experience supporting block-level layout efforts through tapeout
• Prior experience in physical verification and custom layout design, specifically with custom analog layout experience in FINFET 7nm, 5nm, or 3nm
• Prior experience with Cadence Virtuoso or similar custom layout tools

Preferred Qualifications

• Analog & Custom Layout Design: Prior experience in device-level layout techniques (matching, symmetry, shielding, common-centroid, interdigitation, guard rings, isolation structures) and critical design concepts including parasitic control, thermal management, and signal integrity. Custom analog experience in TSMC 2nm or below is a plus.
• EDA Tools & Signoff Flows: Prior experience with EDA tools like Cadence Virtuoso and Calibre (or equivalent) in a Linux environment, with a strong command of physical signoff flows including DRC, LVS, ERC, parasitic extraction, and EM/IR analysis.
• Tapeout & Automation: Prior experience with ASIC/SoC tapeout processes and scripting capabilities (Python, Perl, or TCL) for layout automation.
• Collaboration: Prior experience working with cross-functional teams across multi-location teams.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Message to applicants applying to work in the U.S. and/or Canada

The starting salary range posted for this position is $149,100.00 to $218,100.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.

Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.

U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:

• 10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
• Non-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
• 80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer

For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.

Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:

• .75% of incentive target for each 1% of revenue attainment up to 50% of quota;
• 1.5% of incentive target for each 1% of attainment between 50% and 75%;
• 1% of incentive target for each 1% of attainment between 75% and 100%; and
• Once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.

For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

The applicable full salary ranges for this position, by specific state, are listed below:

New York City Metro Area:

$167,700.00 - $282,000.00

Non-Metro New York state & Washington state:

$149,100.00 - $250,900.00

• For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.

** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.

Cisco is an Affiative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.

Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records.