Senior Analog Engineering Manager

Renesaselectronics; Johns Creek (GA); On-site; USD 210,000 - 290,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics is seeking a Technical Leader to own the architecture and design of DDR5 PHYs and contribute to DDR6-ready architectures. You will guide high-speed datapaths, equalization, and clocking, while driving post-silicon validation and reliability efforts.

A strong background in analog/mixed-signal IC design and leadership is essential. The role requires 12+ years in memory interfaces, with a track record of delivering complex DDR PHY projects and leading teams towards execution

Qualifications

• Advanced degree preferred with 12+ years in analog/mixed-signal IC design.
• Strong leadership and people-management experience in engineering teams.
• Proven track record delivering DDR5/DDR6 or related high-speed memory interfaces.

Responsibilities

• Own DDR5 PHY architecture and DDR6 readiness; guide design and implementation.
• Lead post-silicon bring-up, characterization, debug, and yield improvements.
• Set technical direction and hiring plans for senior engineers.
• Collaborate across SoC, packaging, PCB, validation, and customer teams.

Skills

Technical leadership

Team leadership

Mentorship

Strategic planning

Communication

Education

Electrical Engineering (B.S./M.S.)

PhD preferred

Tools

High-speed IO design

PLL/DLL architectures

Analog/mixed-signal IC design

Memory interface design

Job description

Technical Leadership (DDR5 / DDR6)

Own and guide the architecture, design, and implementation of DDR5 PHYs and contribute to DDR6-ready architectures.

• High-speed TX/RX datapaths
• Advanced equalization, termination, and training circuits
• DLL/PLL-based clocking solutions for multi-GHz operation
• Voltage, reference generation, and power-aware IO design
• Drive closure on timing, jitter, noise, SI/PI, and PVT robustness for aggressive DDR5/DDR6 data rates.

Ensure compliance with JEDEC DDR5 specifications and alignment with evolving DDR6 standards and industry direction.

Lead post-silicon bring-up, characterization, debug, and yield improvement, including lab and customer-system correlation.

People & Organization Leadership

Build, lead, and mentor a team of analog and mixed-signal designers focused on high-speed memory interfaces.

Set technical direction, performance expectations, and development plans for senior and principal engineers.

Drive hiring, onboarding, and team scaling aligned with DDR5 production and DDR6 development needs.

Foster a culture of technical rigor, ownership, and execution excellence.

Program & Cross-Functional Execution

Own DDR5/DDR6 PHY execution balancing schedule, quality, and risk.

Partner closely with: Digital PHY and controller teams SoC integration and system architecture, Package, PCB, SI/PI, and validation teams, Product, program management, and customers.

Interface with foundries, IP vendors, and standards bodies as needed to ensure successful delivery and future readiness.

Methodology, Quality & Roadmap

Establish robust design and signoff methodologies for next-generation high-speed PHYs.

Drive continuous improvement in simulation accuracy, mixed-signal verification, and silicon debug efficiency.

Lead long-term DDR5 sustainment and DDR6 technology roadmap planning, including architectural trade-offs and scaling strategies.

Anticipate challenges from data-rate scaling, power efficiency, and advanced process technologies.

Bachelor's or Master's degree in Electrical Engineering (PhD preferred).

12+ years of experience in analog/mixed-signal IC design with deep focus on high-speed memory interfaces.

5+ years of people-management and technical leadership experience.

Proven hands-on delivery of DDR5 PHYs or late-stage DDR4 designs transitioning to DDR5.

• High-speed IO design and signal integrity
• PLL/DLL and low-jitter clocking architectures
• Mixed-signal verification and silicon validation
• Advanced CMOS process considerations for IOs

Preferred Qualifications

• Direct involvement in DDR6 architectural studies or early-stage development.
• Experience at advanced nodes (7nm, 5nm, and below).
• Background in multi-generation memory PHYs or scalable PHY platforms.
• Ability to lead teams delivering multiple concurrent tape-outs.
• Strong written and verbal communication skills across technical and executive audiences.

Leadership Profile

• High technical credibility with the ability to dive deep when needed
• Strong execution mindset with disciplined risk management
• Effective mentor and team builder
• Strategic thinker with a roadmap-driven approach to DDR evolution
• Comfortable balancing hands-on engagement with organizational leadership

Renesas is an embedded semiconductor solution provider driven by its Purpose, To Make Our Lives Easier . With a global team of over 21,000 engineers and problem solvers in more than 30 countries, we offer the opportunity to work on world‑leading technology for Automotive, Industrial, Infrastructure, and IoT, shaping a safer, healthier, greener, and smarter future.

At Renesas, TAGIE is our culture, grounded in being Transparent, Agile, Global, Innovative, and Entrepreneurial. It shapes how we work, grow and deliver on our purpose together. This collaborative spirit and mindset drive our semiconductor technology to transform industries and impact millions of lives.

We believe in rewarding our employees with a competitive benefits package alongside their salary. More information will be provided during the hiring process.

Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement .

Renesas Electronics deals with dual-use technology that is subject to U.S. export controls regulations. Under these regulations it may be necessary for Renesas to obtain U.S. government export license prior to release of technology to certain persons. The decision whether or not to file or pursue an export license application is at the sole discretion of Renesas.