Senior AI Systems Architect/Researcher

Intel Corporation; Hillsboro (OR); On-site; USD 180,000 - 260,000; Full time

Job summary

Intel Corporation in Hillsboro, OR is seeking a Senior AI Architect/Researcher to translate AI communication and memory bottlenecks into networking architecture and platform direction. You will work across research, architecture, silicon, software, and product teams to shape distributed AI infrastructure.

The role focuses on end-to-end data movement, memory hierarchy, and interconnects to unlock next-order AI efficiency, influence silicon and software roadmaps, and contribute to IP development

Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related STEM field with 5+ years of relevant experience; or PhD in Electrical Engineering, Computer Science, or related field.
• Experience translating AI system bottlenecks into hardware/software architecture is preferred.

Responsibilities

• Analyze AI serving and training workloads to identify communication and memory bottlenecks and translate findings into architectural requirements.
• Drive hardware-software co-design across compute, DPU/IPU, NIC, and SoC fabrics to reflect networking and data movement in AI runtimes and frameworks.
• Define architectural direction for AI systems to move data at scale across xPU-to-xPU, storage, and cross-node paths on IPU/DPU platforms.
• Investigate data-movement bottlenecks across memory hierarchy and interconnects, balancing latency and bandwidth in system design.
• Set multi-generation roadmaps across product lines by aligning research insights with silicon and software roadmaps.

Education

Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related STEM with 5+ years of experience; or PhD in Electrical Engineering or related field

Job description

Job Details:

Job Description:

About Central Engineering Group - Networking Architecture

The CEG Networking Architecture Group defines next-generation networking silicon and platform architecture for hyperscale data centers, cloud infrastructure, and AI workloads. The team focuses on IPU/DPU platforms, advanced packet processing, programmable networking, and the data-movement technologies that enable modern distributed computing systems to scale efficiently.

Position Overview

This role is for a senior AI systems architect who can translate the communication, memory, and orchestration bottlenecks of large-scale AI into networking architecture, IP, and platform direction. The successful candidate will work across research, architecture, silicon, software, and product teams to shape the next generation of distributed AI infrastructure.

As a Senior AI Architect/Researcher, you will help define how AI systems communicate and move data at scale across xPUs, DPUs, IPUs, NICs, memory, and heterogeneous storage. In this pathfinding and research role, you will advance new architectural approaches and translate research insights into network architecture and software capabilities that can influence N+1 to N+3 product roadmap.

The ideal candidate thinks in systems rather than components, understands the memory wall and scale-out serving bottlenecks, and can reason across interconnect, memory hierarchy, software runtime, and compute to unlock the next order of magnitude in AI efficiency. You will help set technical direction and influence silicon and software roadmaps. The candidate is expected to maintain substantial knowledge of state-of-the-art principles and theories, contribute regularly to scientific literature and the research community-at-large, and may participate in the development of Intellectual Property.

Key Responsibilities

Turn Workload Analysis into New IP

• Analyze real AI serving and training workloads, identify communication and memory bottlenecks, and translate those findings into new IP, offload engines, platform features, and architecture requirements


• Drive hardware-software co-design across compute, DPU/IPU, NIC, SoC fabric, and AI serving runtimes, ensuring that networking and data-movement capabilities are reflected in modern inference and training frameworks such as vLLM, SGLang, and others

Architect AI-Scale Networking and Interconnect

• Define the architectural direction for how AI systems and infrastructure move data at scale across xPU-to-xPU, xPU-to-storage, and cross-node paths spanning IPU/DPU platforms, NICs, and heterogeneous storage


• Shape next-generation packet processing, RDMA-class transport, and programmable networking IP that forms the backbone of hyperscale AI inference and training

Attack the Memory Wall and System-Level Bottlenecks

• Investigate the fundamental data-movement bottlenecks in large-scale AI and Agentic inference and training, including KV-cache transfer, disaggregated prefill/decode, model and tensor parallelism, and communication collectives, and translate them into concrete architectural requirements


• Reason across the full memory hierarchy and interconnect to minimize copies, latency, and bandwidth overhead, balancing latency-sensitive control paths against bandwidth-intensive data-paths

Set Roadmap and Lead Across Teams

• Shape multi-generation compute, memory, and interconnect roadmaps across IPU/DPU product lines by defining scaling strategies, migration paths, and architecture requirements that connect research insights to product execution


• Align architecture across networking, SoC fabric, firmware/OS/drivers, and performance modeling teams

What We’re Looking For

To be successful in this role, you should demonstrate the following professional traits:

• Architectural vision - defines long-term strategy across AI systems, networking, memory, and software domains


• Influence without authority - drives alignment across multiple teams and disciplines


• Systems thinking - understands interactions across compute, memory, network, and software


• Decision-making under ambiguity - makes sound tradeoffs with incomplete data


• Collaboration - builds strong cross-functional relationships


• Customer-oriented mindset - translates workload needs into architectural innovations


• Ownership and accountability - drives initiatives end-to-end


• Continuous learning - stays current with evolving AI systems, inference runtimes, interconnects, memory technologies, and cloud infrastructure trends

A strong candidate will have enough depth to reason from first principles, enough practical experience to understand implementation constraints, and enough leadership range to align research, architecture, software, and silicon teams around a coherent direction.

Qualifications:

Minimum Qualifications

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 5+ years of relevant experience; or PhD in Electrical Engineering, Comp