Senior AI Hardware Architect: Power, Security & Chiplets

NVIDIA Corporation; Santa Clara (CA); Vor Ort; USD 184.000 - 357.000; Vollzeit

Benefits dieser Stelle

Equity

Benefits

Zusammenfassung

NVIDIA is seeking an AI Hardware Architect in Santa Clara to design and optimize next‑gen AI hardware, including GPUs and CPUs. You will study workloads, propose microarchitectural solutions, and collaborate with software, firmware, and platform teams to improve performance, power, and security across SOCs.

The role requires a Master’s in CE/EE with 8+ years of relevant experience, strong coding skills, and a deep understanding of LLMs.

Qualifikationen

• Master's degree in Computer Engineering or Electrical Engineering or equivalent experience
• 8+ years of relevant industry experience
• Experience building high performance microarchitectural structures
• Clear understanding of performance, power and security implications of microarchitectural features
• Excellent coding and algorithmic thinking skills
• Good understanding of LLMs

Aufgaben

• Work on groundbreaking GPU and CPU systems
• Analyze and identify areas for improvement across disciplines
• Study applications and models running on Nvidia hardware and their architectural implications
• Develop microarchitectural solutions for connectivity, coherency, power management, security, and memory management
• Collaborate with software, firmware, platform and cross-functional teams on system architecture
• Model, analyze, and explain performance and power advantages
• Guide customers and firmware engineers to optimize performance

Kenntnisse

Microarchitecture

Performance analysis

Power management

Security implications

Communication

Coding

LLMs understanding

Ausbildung

Master's degree in Computer Engineering or Electrical Engineering

Tools

Bus protocols knowledge

Chip design tools

Jobbeschreibung

NVIDIA is seeking an AI Hardware Architect in Santa Clara to design and optimize next‑gen AI hardware, including GPUs and CPUs. You will study workloads, propose microarchitectural solutions, and collaborate with software, firmware, and platform teams to improve performance, power, and security across SOCs.

The role requires a Master’s in CE/EE with 8+ years of relevant experience, strong coding skills, and a deep understanding of LLMs.