Semiconductor Digital Architect, Texas Institute for Electronics

University of Texas at Austin; Austin (TX); Hybrid; USD 150,000 - 210,000; Full time

Benefits offered by this job

Competitive health benefits

Tuition assistance

LinkedIn Learning access

Professional conference opportunities

Flexible spending accounts

Job summary

University of Texas at Austin seeks a Semiconductor Digital Architect to develop next-gen digital subsystems for 2.5D/3D microsystems, enabling high-bandwidth AI, HPC, and wireless acceleration. You will define architecture specs, optimize dataflows, and collaborate with industry partners.

You will mentor teams on RTL methodologies, IP integration, and verification for multi-die systems, translating innovations into roadmaps and reference designs.

Qualifications

• Master's degree in Electrical or Computer Engineering.
• 12+ years in digital/system architecture for SoC/FPGA/ASIC with AI/HPC exposure.
• Deep expertise in dataflow, memory, interconnects, and compute optimization.
• RTL design/verification experience; HW/SW co-design; FPGA prototyping.
• Proficient in performance modeling and architectural trade-off analysis.
• Strong collaboration with packaging, EDA, and process teams.
• Proven track record delivering complex digital design programs.
• Austin, TX location preferred; hybrid work with travel up to 30–50%.

Responsibilities

• Architect next-gen digital subsystems for 2.5D/3D microsystems.
• Define, optimize architecture specs, dataflows and interconnects.
• Co-optimize with EDA, packaging, and system modeling teams.
• Lead system-level modeling and design-space exploration for AI/HPC.
• Engage with industry partners to shape ecosystem directions.
• Mentor RTL methodologies, IP integration, verification for multi-die.
• Translate innovations into roadmaps and reference designs.
• Other related functions as assigned.

Skills

Digital architecture

SoC/FPGA/ASIC

Dataflow architectures

Memory hierarchies

Interconnects

Compute optimization

RTL design/verification

HW/SW co-design

FPGA prototyping

Performance modeling

SystemC/C++/Python

Cross-functional collaboration

Program delivery

Education

Master's in Electrical or Computer Engineering

Tools

SystemVerilog/VHDL

C++/Python

Job description

Job Posting Title:

Semiconductor Digital Architect, Texas Institute for Electronics

Hiring Department:

Texas Institute for Electronics

Position Open To:

All Applicants

Weekly Scheduled Hours:

40

FLSA Status:

To Be Determined at Offer

Earliest Start Date:

Ongoing

Position Duration:

Expected to Continue

Location:

AUSTIN, TX

Job Details:

General Notes

About TIE

Texas Institute for Electronics (TIE) is a transformative, well-funded semiconductor foundry venture combining the agility of a startup with the scale of a national initiative.

Our Mission

A key part of our mission is to advance the state of the art in 3D heterogeneous integration (3DHI), chiplet-based architectures, and multi-component microsystems- catalyzing breakthroughs across microelectronics, artificial intelligence, quantum computing, high-performance computing, and next-generation healthcare devices.

Our Impact

Backed by $1.4 billion in combined funding from DARPA, Texas state initiatives, and strategic partners, we are building foundational capabilities in advanced packaging and integrated design infrastructure to restore U.S. leadership in microelectronics manufacturing.

Our Technology

Our 3DHI and chiplet integration platforms integrate novel thermal management and advanced interconnect solutions to deliver unprecedented performance and energy efficiency. Operating at the intersection of defense electronics and commercial markets, TIE offers a rare opportunity to reimagine an industry from the ground up and build transformative products with global impact.

UT Austin, recognized by Forbes as one of America's Best Large Employers, provides outstanding employee benefits and total rewards packages that include:

• Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
• Voluntary Vision, Dental, Life, and Disability insurance options
• Generous paid vacation, sick time, and holidays
• Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
• Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
• Flexible spending account options for medical and childcare expenses
• Robust free training access through LinkedIn Learning plus professional conference opportunities
• Tuition assistance
• Expansive employee discount program including athletic tickets
• Free access to UT Austin's libraries and museums with staff ID card
• Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
• For more details, please see Benefits | Human Resources and UT Austin Employee Experience | Human Resources and UT Austin Employee Experience | Human Resources

Purpose

The purpose of the Semiconductor Digital Architect is to develop next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems, enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms. This includes defining architecture specifications, collaborating with teams to optimize performance, and engaging with semiconductor industry partners to shape ecosystem directions.

Responsibilities

• Architect next-generation digital subsystems and compute fabrics for 2.5D/3D microsystems-enabling scalable, high-bandwidth integration across AI, HPC, and wireless acceleration platforms.
• Define and optimize architecture specifications, dataflows, and interconnect topologies (chiplet fabrics, NoCs, HBM, PCIe/CXL) across heterogeneous dies.
• Collaborate with EDA, packaging, and system modeling teams to co-optimize digital architectures for performance, power, and reliability.
• Lead system-level modeling and design-space exploration for AI and signal-processing workloads using simulation and prototyping frameworks.
• Engage with industry partners and standards bodies (UALink, NVLink Fusion, UltraEthernet, CXL 3.x) to shape ecosystem directions.
• Mentor internal design teams on RTL methodologies, IP integration, and verification best practices for multi-die systems.
• Translate architectural innovations into roadmaps and reference designs, driving alignment between research, productization, and customer enablement.
• Other related functions as assigned.

Required Qualifications

• Master's of Science in Electrical or Computer Engineering.
• 12 years of experience in digital or system architecture for SoC/FPGA/ASIC designs, with strong exposure to AI, networking, or HPC accelerators.
• Deep expertise in dataflow architectures, memory hierarchies, interconnects, and compute optimization.
• Hands-on experience with RTL design/verification (SystemVerilog/VHDL), hardware-software co-design, and FPGA prototyping.
• Proficiency in performance modeling and architectural trade-off analysis (SystemC, C++, or Python-based frameworks).
• Strong cross-disciplinary collaboration-able to interface with packaging, EDA, and process engineering teams.
• Proven record of delivering complex digital design programs from concept through execution.
• Location. Austin, Texas is preferred for close collaboration with our engineering teams and partners. Hybrid work arrangements may be possible, with travel up to 30-50% as needed. Any flexible arrangement would be subject to university policies and approval regarding employment laws and regulations.

Preferred Qualifications

• PhD. D in in Electrical or Computer Engineering and ten or more years of experience in digital or system architecture for SoC/FPGA/ASIC designs, with strong exposure to AI, networking, or HPC accelerators.
• Prior architecture experience at AI or semiconductor computer companies.
• Familiarity with heterogeneous (multi-materials and/or multi-function) compute integration and multi-die packaging (2.5D/3D, hybrid bonding, interposers).
• Experience with AI/ML or 5G/6G hardware acceleration, linear algebra, and signal-processing architectures.
• Knowledge of interconnect and chiplet standards (BoW, UCIe, CXL, NVLink, UALink) and their ecosystem enablement.
• Track record of publications, patents, or industry leadership in digital or system architecture.
• Excellent technical writing and presentation skills for cross-functional and customer-facing collaboration.

Salary Range

TIE pays industry-competitive salaries.

Working Conditions

• May work around standard office conditions
• Repetitive use of a keyboard at a workstation
• Use of manual dexterity (ex: using a mouse)

Work Shift

• Monday - Friday 8am to 5pm, or flexible between 7am and 6pm.
• Hybrid work arrangements may be possible, with travel up to 30-50% as needed. Any flexible arrangement would be subject to university policies and approval regarding employment laws and regulations.

Required Materials

• Resume/CV
• 3 work references with their contact information; at least one reference should be from a supervisor
• Letter of interest

Employment Eligibility

Regular staff who have been employed in their current position for the last six continuous months are eligible for openings being recruited for through University-Wide or Open Recruiting, to include both promotional opportunities and lateral transfers. Staff who are promotion/transfer eligible may apply for positions without supervisor approval.

Retirement Plan Eligibility

The retirement plan for this position is Teacher Retirement System of Texas (TRS), subject to the position being at least 20 hours per week and at least 135 days in length. This position may have the option to elect the Optional Retirement Program (ORP) instead of TRS, dependent upon the job profile you qualify for, and subject to the position being 40 hours per week and at least 135 days in length.

Background Checks

A criminal history background check will be required for finalist(s) under consideration for this position.

Equal Opportunity Employer

The University of Texas at Austin, as an equal opportunity/affirmative action employer,complies with all applicable federal and state laws regarding nondiscrimination and affirmative action. The University is committed to a policy of equal opportunity for all persons and does not discriminate on the basis of race, color, national origin, age, marital status, sex, sexual orientation, gender identity, gender expression, disability, religion, or veteran status in employment, educational programs and activities, and admissions.

Pay Transparency

The University of Texas at Austin will not discharge or in any other manner discriminate against employees or applicants because they have inquired about, discussed, or disclosed their own pay or the pay of another employee or applicant. However, employees who have access to the compensation information of other employees or applicants as a part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information, unless the disclosure is (a) in response to a formal complaint or charge, (b) in furtherance of an investigation, proceeding, hearing, or action, including an investigation conducted by the employer, or (c) consistent with the contractor's legal duty to furnish information.

Employment Eligibility Verification

If hired, you will be required to complete the federal Employment Eligibility Verification I-9 form. You will be required to present acceptable and original documents to prove your identity and authorization to work in the United States. Documents need to be presented no later than the third day of employment. Failure to do so will result in loss of employment at the university.

E-Verify

The University of Texas at Austin use E-Verify to check the work authorization of all new hires effective May 2015. The university's company ID number for purposes of E-Verify is 854197. For more information about E-Verify, please see the following:

• E-Verify Poster (English and Spanish) [PDF]
• Right to Work Poster (English) [PDF]
• Right to Work Poster (Spanish) [PDF]

Compliance

Employees may be required to report violations of law under Title IX and the Jeanne Clery Disclosure of Campus Security Policy and Crime Statistics Act (Clery Act). If this position is identified a Campus Security Authority (Clery Act), you will be notified and provided resources for reporting. Responsible employees under Title IX are defined and outlined in HOP-3031.

The Clery Act requires all prospective employees be notified of the availability of the Annual Security and Fire Safety report. You may access the most recent report here or obtain a copy at University Compliance Services, 1616 Guadalupe Street, UTA 2.206, Austin, Texas 78701.