[Samsung Electronics America] DFx Engineer 채용

Samsung Electronics America; United States; On-site; USD 180,000 - 270,000; Full time

Job summary

Samsung Austin Research and Development Center (SARC/ACL) seeks a seasoned DFx engineer to drive DFT architecture from RTL to silicon, across GPU and interconnect IP, with a focus on test coverage and fast tapeouts. This on-site role is based in Austin, TX, with collaboration across global teams.

Ideal candidates bring 10+ years of DFx experience, multiple tapeouts, and strong communication to partner with RTL, SOC, STA, and PD teams. Base pay ranges from $180,200 to $270,400 per year.

Qualifications

• 10+ years of DFx experience (or 8+ with Master’s, or 6+ with PhD)
• DFx expertise across multiple tapeouts for digital IP/SOC projects
• Architect DFT solutions from scratch with detailed specs
• Deep understanding of test coverage across scan modes for bleeding-edge nodes
• Strong RTL coding & STA knowledge with Physical Design familiarity
• Experience with multi-voltage/multi-clock domain implementation a plus
• Experience with hierarchical DFT and streaming fabric
• Strong post-silicon debugging skills and ability to resolve silicon issues
• Excellent written and verbal communication with global stakeholders
• Thrives in fast-paced yearly tapeout cycles

Responsibilities

• Define the DFT scan architecture from RTL to silicon
• Create implementation specs detailing SOC interfaces, clocks, and test/debug modes
• Collaborate with DFX/RTL/SOC/STA/PD teams to finalize specifications
• Implement DFT scan: RTL creation, LINT, timing-constraints, ATPG and simulation
• Benchmark test-coverage and test-time against expectations
• Drive ongoing DFX improvements: expand coverage and reduce test-time
• Resolve silicon issues, including test escapes and yield loss
• Work with SOC and Product/Test teams to ensure smooth defect resolution

Skills

DFx expertise

DFT architecture

RTL/STA familiarity

Post-silicon debugging

Stakeholder communication

Team collaboration

Education

Bachelor’s in CS/CE

Master’s degree

PhD

Job description

Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!Role and ResponsibilitiesAs a seasoned DFx engineer, you will be involved across the entire spectrum of activities all the way from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug.  You will be working on IP-level projects (GPU, system interconnect) in bleeding-edge processes that continually drive high test-coverage requirements. This position is local to Austin, TX only.You understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, and execution.  You create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/debug modes.  You close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams.You implement DFT scan:  RTL creation, LINT, timing-constraints, ATPG and simulation.   Benchmark test-coverage and test-time to ensure that they meet expectations.  You drive towards continuing DFX excellence:  improving test-coverage, minimizing test-time, and exploring tools / methods that improve execution efficiency.You build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve any silicon issues including test-escapes and yield loss.Skills and Qualifications10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projectsDemonstrated ability to architect DFT solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation.Detailed understanding of test-coverage requirements across various scan modes especially as they pertain to bleeding-edge process nodes. Strong familiarity with RTL coding & STA with working knowledge of Physical DesignFamiliarity with multi-voltage and multi-clocking domain implementation is a plus.Exposure to advanced approaches including hierarchical DFT and streaming fabric.Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues.Is able to solve difficult problems with creative solutions or analysis.Crisp written and oral communication skills including working with global stakeholdersThrives in fast-paced environment:   i.e. yearly project tapeoutsOur Team We’re strengthening our team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Xclipse GPU is the first mobile GPU with ray tracing technology that enables console-level graphic for Samsung Galaxy smartphones. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.Our Physical Design group is part of the larger Design Implementation team at SARC/ACL. The fast-paced environment here provides us opportunities to learn different areas of design implementation and diversifying our technical expertise. We take pride in our highly collaborative team culture and feel supported by our leadership to explore new ideas and bring them to reality everyday. We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow.Total RewardsAt Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Samsung employees have access to benefits including medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation.Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.U.S. Export ControlThis role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a seasoned DFx engineer, you will be involved across the entire spectrum of activities all the way from defining the DFT scan architecture through implementation and culminating in pattern generation including silicon debug. You will be working on IP-level projects (GPU, system interconnect) in bleeding-edge processes that continually drive high test-coverage requirements. This position is local to Austin, TX only.

You understand SOC requirements and project milestones to help define a DFT architecture which optimally balances between coverage, test-time, and execution.

You create a detailed implementation spec which documents details of the architecture including SOC-level interface, clock design, and support of various test/debug modes.

You close on the spec with stakeholders including DFX / RTL / SOC / STA / PD teams.

You implement DFT scan: RTL creation, LINT, timing-constraints, ATPG and simulation. Benchmark test-coverage and test-time to ensure that they meet expectations.

You drive towards continuing DFX excellence: improving test-coverage, minimizing test-time, and exploring tools / methods that improve execution efficiency.

You build strong collaboration with SOC and Product/Test Engineering teams to quickly resolve any silicon issues including test-escapes and yield loss.

Skills and Qualifications

• 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
• 10+ years of DFx expertise encompassing multiple tapeouts for digital IP (CPU / GPU) and/or SOC projects
• Demonstrated ability to architect DFT solutions from scratch on at least 1 project, and to create detailed specifications that can be used as a blueprint for implementation.
• Detailed understanding of test-coverage requirements across various scan modes especially as they pertain to bleeding-edge process nodes.
• Strong familiarity with RTL coding & STA with working knowledge of Physical Design
• Familiarity with multi-voltage and multi-clocking domain implementation is a plus.
• Exposure to advanced approaches including hierarchical DFT and streaming fabric.
• Strong post-silicon experience as it relates to debugging silicon behavior and test-escape issues. Is able to solve difficult problems with creative solutions or analysis.
• Crisp written and oral communication skills including working with global stakeholders
• Thrives in fast-paced environment: i.e. yearly project tapeouts

Our Team

We’re strengthening our team of talented individuals with diverse skill sets to build a technology roadmap and deliver market-leading GPU. Our Xclipse GPU is the first mobile GPU with ray tracing technology that enables console-level graphic for Samsung Galaxy smartphones. With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.

Our Physical Design group is part of the larger Design Implementation team at SARC/ACL. The fast-paced environment here provides us opportunities to learn different areas of design implementation and diversifying our technical expertise. We take pride in our highly collaborative team culture and feel supported by our leadership to explore new ideas and bring them to reality everyday. We believe in connecting your area of expertise with the right level and functional discipline that can empower you to grow.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

Samsung employees have access to benefits including medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

Trade Secrets

By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

U.S. Export Control

This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.