[Samsung Electronics America] Senior Staff Engineer, Physical Design (Floorplanning) 채용

Bzpp; United States; On-site; USD 180,000 - 270,000; Full time

Job summary

Samsung in Austin, TX is seeking a Senior Staff GPU Physical Design Engineer to shape full-chip and block-level implementation, focusing on top-level floorplanning and power-grid integration for high-performance GPU IP. You will collaborate with architecture RTL, advanced design technology, and external vendors to resolve complex challenges and deliver robust silicon across advanced nodes.

This senior IC role emphasizes leadership, methodology innovation, and mentoring, with a strong focus on

Qualifications

• 11+ years of experience with full physical design flows.
• Expertise in top-level floorplanning and low-power design.
• Proficient with PNR/physical-design tools and scripting.

Responsibilities

• Lead top-level floorplanning for GPU/SoC designs.
• Design and validate power-grid implementation and routing.
• Drive automation and methodology improvements across projects.
• Mentor junior engineers and promote continuous learning.

Skills

Senior hardware design

GPU/SoC floorplanning

Power-grid design

Education

Bachelor's or higher in CS/Engineering

Tools

FusionCompiler

Innovus

ICC2

PrimeTime

Tempus

StarRC

RedHawk

Job description

Position SummarySamsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!Role and ResponsibilitiesAs a Senior Staff GPU Physical Design Engineer, you will help shape the physical implementation and methodology innovation for high-performance GPU and system-level IP, enabling market-differentiating power, performance, and area (PPA) goals across Samsung’s advanced technology nodes. Your work will impact implementation quality, silicon readiness, and scalable execution for next-generation GPU IPs.In this senior individual contributor role, you will contribute to key stages of the physical design flow, with a particular focus on top-level floorplanning (chip-level or large-IP planning) and power-grid implementation, while helping advance implementation strategies, methodology innovation, and scalable execution across parallel development cycles. You will collaborate closely with hardware, advanced design technology, and system-level teams to resolve complex implementation challenges and deliver robust, high-quality silicon for advanced-node designs.Leveraging your expertise in one or more technical areas, you help shape full-chip and block-level implementation, including top-level floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs.You contribute to implementation strategies to achieve market-differentiating PPA targets, including power-grid design and implementation, power optimization, congestion management, STA-driven convergence, and reliability considerations across advanced-node designs.You help advance methodology and flow innovation, including automation, tool optimization, and scalable design practices, including developing or rewriting physical design flows, to improve implementation quality, productivity, and repeatability across projects.You collaborate cross functionally with architecture, RTL, advanced design technology, software, system-level teams, and external vendors, influencing top-level floorplanning decisions and providing technical guidance to block implementers, to align design assumptions and resolve complex implementation challenges across advanced-node programs.You inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation, and promoting continuous learning by staying ahead of physical design innovation for emerging GPU technologies.Skills and Qualifications11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.7+ years of hands-on experience with full physical design implementation flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff.Strong expertise in top-level floorplanning for complex GPU or SoC designs, low-power design, physical verification (DRC/LVS), and advanced-node challenges.Hands-on power-grid design and implementation experience using PNR tools (FusionCompiler, Innovus or equivalent)Proficiency in power-grid robustness analysis using (RedHawk or equivalent)Experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerationsStrong proficiency with industry-standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)Strong proficiency with PNR/physical-design tools, commands, and toolflows.Strong scripting and automation skills in Python, Tcl, Shell, or PerlStrong analytical, debugging, and problem-solving skills with a data-driven approach for complex flow and design challengesExperience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers.Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.Preferred QualificationsPackage and power-only layer experience is a plus.Experience with advanced-node designs (≤5nm) and high-performance GPU or SoC programsExperience with DTCO methodologies and implementation scalability challengesLow-power partitioning, congestion awareness, layout-integration and feed-through/pin management experience.Automation/flow-level methodology (beyond ad-hoc scripting).Experience with floorplanning methodologies and physical-design tradeoffs.Our Team The Advanced Design Technology and Design Implementation teams play a critical role in enabling GPU and system-level development within Samsung SARC/ACL and the broader System LSI organization. Operating at the intersection of design technology and physical implementation, we partner closely with Foundry from early technology exploration through the full development cycle. Spanning advanced design methodologies, GPU physical design, CAD, and DTCO, we accelerate adoption of leading technology nodes and deliver optimized power, performance, area (PPA), silicon quality, and turnaround time for next-generation IP solutions.You will join a highly collaborative, fast-paced environment working across parallel development cycles with direct impact on consumer technologies used worldwide. Here, you’ll help build what’s next: experimenting with new ideas, broadening your technical expertise, and solving impactful challenges alongside talented teammates who value ownership, continuous learning, and growth.Total RewardsAt Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location.Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation.This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Trade Secrets By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.U.S. Export ControlThis role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.#SARC #ACL

Senior Staff Engineer, Physical Design (Floorplanning)

Senior Staff Engineer, Physical Design (Floorplanning)

• Physical Design
• Floorplanning
• GPU
• Semiconductor
• EDA Tools
• Automation

• 접수기간

  2026.07.30 ~ 2026.10.30

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world. Come build with us!

Role and Responsibilities

As a Senior Staff GPU Physical Design Engineer, you will help shape the physical implementation and methodology innovation for high-performance GPU and system-level IP, enabling market-differentiating power, performance, and area (PPA) goals across Samsung’s advanced technology nodes. Your work will impact implementation quality, silicon readiness, and scalable execution for next-generation GPU IPs.

In this senior individual contributor role, you will contribute to key stages of the physical design flow, with a particular focus on top-level floorplanning (chip-level or large-IP planning) and power-grid implementation, while helping advance implementation strategies, methodology innovation, and scalable execution across parallel development cycles. You will collaborate closely with hardware, advanced design technology, and system-level teams to resolve complex implementation challenges and deliver robust, high-quality silicon for advanced-node designs.

Leveraging your expertise in one or more technical areas, you help shape full-chip and block-level implementation, including top-level floorplanning, placement, routing, timing closure, and signoff for complex GPU and SoC designs.

You contribute to implementation strategies to achieve market-differentiating PPA targets, including power-grid design and implementation, power optimization, congestion management, STA-driven convergence, and reliability considerations across advanced-node designs.

You help advance methodology and flow innovation, including automation, tool optimization, and scalable design practices, including developing or rewriting physical design flows, to improve implementation quality, productivity, and repeatability across projects.

You collaborate cross functionally with architecture, RTL, advanced design technology, software, system-level teams, and external vendors, influencing top-level floorplanning decisions and providing technical guidance to block implementers, to align design assumptions and resolve complex implementation challenges across advanced-node programs.

You inspire high performance by mentoring junior engineers, fostering a culture of ownership, accountability and innovation, and promoting continuous learning by staying ahead of physical design innovation for emerging GPU technologies.

Skills and Qualifications

• 11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
• 7+ years of hands-on experience with full physical design implementation flows, including synthesis, place-and-route, clock tree synthesis (CTS), timing closure, and signoff.
• Strong expertise in top-level floorplanning for complex GPU or SoC designs, low-power design, physical verification (DRC/LVS), and advanced-node challenges.
• Hands-on power-grid design and implementation experience using PNR tools (FusionCompiler, Innovus or equivalent)
• Proficiency in power-grid robustness analysis using (RedHawk or equivalent)
• Experience with timing analysis and convergence methodologies, including STA, signal integrity, and reliability considerations
• Strong proficiency with industry-standard EDA tools (Synopsys or Cadence: ICC2/Fusion Compiler or Innovus, PrimeTime/Tempus, StarRC)
• Strong proficiency with PNR/physical-design tools, commands, and toolflows.
• Strong scripting and automation skills in Python, Tcl, Shell, or Perl
• Strong analytical, debugging, and problem-solving skills with a data-driven approach for complex flow and design challenges
• Experience with leading technical initiatives, driving process and methodology innovation, and mentoring engineers.
• Excellent collaboration and communication skills, with the ability to navigate ambiguity and influence stakeholders in a fast-paced, global team environment.

Preferred Qualifications

• Package and power-only layer experience is a plus.
• Experience with advanced-node designs (≤5nm) and high-performance GPU or SoC programs
• Experience with DTCO methodologies and implementation scalability challenges
• Low-power partitioning, congestion awareness, layout-integration and feed-through/pin management experience.
• Automation/flow-level methodology (beyond ad-hoc scripting).
• Experience with floorplanning methodologies and physical-design tradeoffs.

Our Team

The Advanced Design Technology and Design Implementation teams play a critical role in enabling GPU and system-level development within Samsung SARC/ACL and the broader System LSI organization. Operating at the intersection of design technology and physical implementation, we partner closely with Foundry from early technology exploration through the full development cycle. Spanning advanced design methodologies, GPU physical design, CAD, and DTCO, we accelerate adoption of leading technology nodes and deliver optimized power, performance, area (PPA), silicon quality, and turnaround time for next-generation IP solutions.

You will join a highly collaborative, fast-paced environment working across parallel development cycles with direct impact on consumer technologies used worldwide. Here, you’ll help build what’s next: experimenting with new ideas, broadening your technical expertise, and solving impactful challenges alongside talented teammates who value ownership, continuous learning, and growth.

Total Rewards

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,200 and $270,400. Your actualbase pay will depend on variables that may includeyour educationskills, qualifications, experience, and worklocation.

Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in long term incentive plan and relocation.

This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).

Trade Secrets

By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.

U.S. Export Control

This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.

#SARC #ACL