Rust Engineer

Platform Recruitment; San Francisco (CA); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Platform Recruitment is seeking Rust engineers to help build silicon for high-performance GenAI. You’ll work on a custom, cycle-accurate model written in Rust, validating architecture and RTL, with hardware-driven design flows and AI tooling.

The team values versatile engineers who move between core modelling, tooling, and testing, and who can contribute to retrieval, knowledge graphs, and automated reasoning within the flow. Hybrid Bay Area role with travel expected.

Qualifications

• Production-level Rust experience shipping real systems.
• 3+ years of engineering experience with clean, well-tested code and CI practices.
• Genuine interest in hardware and ability to ramp up quickly.
• Based in the Bay Area with hybrid work or travel as needed.

Responsibilities

• Build and extend internal infrastructure and tooling in Rust to support hardware and software teams
• Design and implement the Rust-based simulator that underpins the verification flow
• Build the host-side interface library connecting software and hardware layers
• Write targeted and randomized tests to surface corner cases and rare event sequences
• Partner across hardware, architecture and software teams to translate specifications into testable properties

Skills

Rust

System programming

CI/CD

Hardware interest

Job description

We're working with a well-funded, highly selective AI infrastructure startup building silicon for large-scale AI inference and training. Founded by veteran chip architects who previously led a major AI hardware program at a top tech company, the business has grown fast and is backed by top-tier investors.

They're looking for Rust engineers to help build best-in-class silicon for high-performance, sustainable GenAI, across compute, memory management, and high-speed connectivity.

The Role

The environment here is genuinely unusual for a Rust role: a custom, code-generated cycle-accurate model, built in Rust, sits at the center of the whole design flow, feeding architecture validation, RTL validation, and post-silicon validation, with hardware description largely generated from this model rather than handwritten. You'd work on the simulator and host-side interface library that make up this model, alongside writing the targeted and randomized tests that stress it. The team is also building AI directly into the flow itself, including retrieval, knowledge-graph, and automated-reasoning tooling.

Scope isn't fixed here — they want versatile engineers who can move between core modelling, tooling, and testing rather than staying in one lane.

Responsibilities

• Build and extend internal infrastructure and tooling in Rust to support hardware and software teams
• Design and implement the Rust-based simulator that underpins the verification flow
• Build the host-side interface library connecting software and hardware layers
• Write targeted and randomized tests to systematically surface corner cases and rare event sequences
• Partner across hardware, architecture and software teams to translate specifications into concrete, testable properties

Requirements

• Production-level Rust experience — you've shipped real systems and are comfortable with ownership, traits, generics with bounds, and enums as sum types
• 3+ years of engineering experience with strong fundamentals: clean, well-tested, well-documented code, and comfort with build systems, version control and CI
• Genuine interest in hardware and willingness to ramp up quickly
• Remote (with travel) or hybrid, based in the Bay Area

Nice to Have

• Hands-on hardware experience in any form — FPGA, embedded systems, robotics, or prior hardware-adjacent roles; accelerator experience is a strong plus
• Experience with foreign function interfaces (Rust FFI ideal, any cross-language experience valuable)
• Exposure to formal methods, model checking or property-based testing (e.g. proptest, Kani)
• Understanding of computer architecture: pipelines, caches, memory hierarchies, on-chip interconnects
• Familiarity with ML systems/frameworks

What Sets This Role Apart

• Tool-building culture: the design flow is built in-house, generated from a custom modelling layer rather than relying on legacy, vendor-driven methodology
• AI-native flow: active work integrating AI tooling (retrieval, knowledge graphs, automated reasoning) directly into design and verification
• Real ownership: your work feeds directly into production silicon at a company scaling fast
• Flexible scope: significant freedom to shape what you work on, from core modelling and tooling through to deeper architecture involvement

Package & Process

Compensation is highly competitive, with strong equity and full benefits.