RTL Designer

HRB; United States; Remote; USD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking organization as an RTL Designer, where your expertise in hardware architecture and RTL programming will drive innovation in ASIC and FPGA development. In this dynamic role, you'll collaborate with a talented team to design and implement cutting-edge hardware solutions, utilizing Agile methodologies to ensure efficient project delivery. Your strong analytical skills and hands-on experience with PCIe PHY integration will be crucial in overcoming complex challenges. This is a unique opportunity to make a significant impact in a thriving environment that values creativity and critical thinking.

Qualifications

• 5+ years of experience in hardware systems design and RTL performance analysis.
• Expertise in FPGA/ASIC development and debugging.

Responsibilities

• Design and oversee hardware architectures and RTL modules.
• Simulate, test, and debug hardware designs.

Skills

RTL Design

Verilog/SystemVerilog

Python

Agile Methodologies

PCIe PHY and Controller Integration

Education

B.S in Electrical Engineering

M.S in Electrical Engineering

Ph.D in Electrical Engineering

Tools

FPGA Development Tools

ASIC Development Tools

Job description

To help grow our organization, we are looking for anRTL Designerto contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

• • Design, propose, and oversee the analysis/evaluation of hardware architectures
  • Design and code RTL modules written in Verilog/SystemVerilog
  • Simulate and perform hardware-based testing, debug, and verification
  • Scripting and basic software development in support of hardware design
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements

• • B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
  • 5+ years of experience in hardware systems design, analyzing and improving RTL hardware performance and area as well as lab bring-up
  • FPGA/ASIC development environment tools expertise, including design, implementation and debug
  • Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
  • Ability to read and write code in Python (C, C++ are assets)
  • Hands on experience in PCIe PHY and controller IP integration and bring-up

Preferred Skills & Experience

• • Deep experience with ASIC and FPGA programming including timing closure, resource management, and using IP libraries highly preferred
  • Working experience with PCIe, UCIe, and HBM will be an asset
  • Experience with Agile development methodologies
  • Experience in technical leadership of small teams