RISC-V Performance Infrastructure Engineer (Hybrid)

Tenstorrent Inc.; Texas; Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent Inc. is seeking a Sr. Engineer to design and run the performance infrastructure shared by RISC-V teams. You will build benchmarking automation, capture workloads, and enable efficient analysis across silicon, FPGA and models.

You will contribute to SimPoint generation and data-driven dashboards, integrating open tools into production workflows while collaborating with CPU performance and software engineers.

Qualifications

• Strong Python and shell scripting skills.
• Experience in Linux system administration and lab hardware.
• Experience automating at scale (job scheduling, artifacts, databases).
• CI pipelines and container workflows (GitLab).

Responsibilities

• Build benchmarking automation and CI pipelines that run workloads across silicon, FPGA/emulation platforms and models.
• Own SimPoint generation and management infrastructure.
• Build and integrate performance data collection into databases with dashboards.
• Develop workload capture and replay tooling (QEMU- and CRIU-based checkpointing).
• Collaborate with performance and software engineers to remove infrastructure friction.

Skills

Python

Shell scripting

Linux systems

CI (GitLab)

Containerization

Automation at scale

Job scheduling

Databases

Dashboards

Tools

QEMU

CRIU

Job description

Sr. Engineer, Performance Infrastructure (RISC-V)

Australia; Santa Clara, California, United States

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a talented engineer to build and run the performance infrastructure across RISC-V hardware and software. This is the plumbing that both teams' performance work stands on — benchmarking automation, data collection, and workload capture across silicon, FPGA/emulation platforms and performance models. You'll work across both teams, enabling performance and software engineers to spend their time on analysis and optimization instead of running experiments by hand.

This role is remote, based out of the US or Australia, can also be hybrid from Austin, TX or Santa Clara, CA.

We welcome candidates at various experience levels. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• Great at identifying problems and developing solutions, with a bias toward owning the systems you build.
• Enjoys building tools and optimizing workflows so other engineers can move faster.
• Strong Linux systems engineer, comfortable wrangling lab machines, clusters and flaky hardware platforms.
• Skilled in Python and shell scripting, with solid CI (GitLab) and container experience.
• Experienced automating at scale — job scheduling, artifact management, databases and dashboarding; curiosity about CPU performance is a plus, deep microarchitecture background is not required.

What We Need

• Build and maintain benchmarking automation and CI pipelines that run SPEC and real-world workloads across RISC-V silicon, FPGA/emulation platforms and performance models.
• Own SimPoint generation and management infrastructure.
• Build performance-data collection into databases, with dashboards and visualization tools on top, so trends and regressions are visible without manual effort.
• Develop workload capture and replay tooling (QEMU- and CRIU-based checkpointing) so perf engineers can trace and analyze workloads reproducibly.
• Collaborate closely with performance and software engineers on both teams to understand their flows and remove the infrastructure friction from them.

What You Will Learn

• End-to-end exposure to CPU performance work, from workload capture through analysis and convergence.
• Hands-on experience with pre-silicon and post-silicon performance platforms — models, emulation, FPGA and real RISC-V hardware.
• Integration of open-source and industry-standard tools into production-grade flows.
• Work in a deeply technical, highly collaborative team solving cutting-edge CPU and AI challenges.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

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