RFIC Layout Engineer

Apple; Austin (TX); On-site; USD 80,000 - 130,000; Full time

Job summary

Ein innovatives Unternehmen sucht einen RFIC Layout Engineer, der leidenschaftlich daran interessiert ist, RF-Analogschaltungen in fortschrittlichen Technologie-Knoten zu integrieren. In dieser spannenden Rolle werden Sie tägliche Layout-Herausforderungen meistern und eng mit Design- und Layout-Teams zusammenarbeiten, um Produkte zu verbessern und die Benutzererfahrung weltweit zu optimieren. Sie werden die Verantwortung für das detaillierte Layout von benutzerdefinierten Blöcken übernehmen und Lösungen zur Optimierung von Layout-Aufgaben vorschlagen. Wenn Sie ein kreativer Problemlöser sind und in einem dynamischen Umfeld arbeiten möchten, ist dies die perfekte Gelegenheit für Sie.

Qualifications

• 3+ Jahre Erfahrung in der RFIC Layout-Entwicklung.
• Tiefes Wissen über sub-mikron CMOS-Technologien.

Responsibilities

• Verantwortlich für das Layout von benutzerdefinierten Blöcken für Hochfrequenz-RF-Schaltungen.
• Verifizieren und Verfeinern von Layouts durch Simulation zur Erfüllung der Entwurfsanforderungen.

Skills

CMOS Technologien

RF Layout Methodologien

DRC, LVS, ERC Verifikation

Hochfrequenz Routing

Education

Bachelorabschluss

Tools

Cadence

Calibre

Job description

RFIC Layout Engineer

Location: Austin, Texas, United States

Department: Hardware

Summary

Posted: May 08, 2025

Role Number: 200603235

Are you passionate about advancing RF analog circuit integration in advanced technology nodes for wireless transceivers? Do you thrive on innovation and improving RF layout methodologies? As an RFIC Layout Engineer, you will tackle daily layout challenges, collaborate with RFIC design and layout teams, and work to improve products to surpass previous iterations and enhance user experiences worldwide.

Description

You will be responsible for laying out detailed custom blocks, including floorplanning, placement, routing, and verification for high-frequency RF circuits. You will verify and refine layouts through simulation to meet design requirements, diagnose verification issues (DRC/LVS) using Cadence and Calibre, and collaborate closely with engineering teams to understand design constraints and opportunities. You will also propose solutions to streamline layout tasks and help define methodologies.

Minimum Qualifications

• BS degree with 3+ years of industry experience
• Deep knowledge of sub-micron CMOS technologies (16nm, 7nm, and beyond) and proficiency with FinFET structures, guard rings, deep N-wells, and PN junctions
• Familiarity with process effects such as LOD, WPE, and DFM
• Understanding of trade-offs involving matching, parasitics, high-frequency routing, isolation, coupling, shielding, RC delay, EM, IR, ESD, and latch-up

Preferred Qualifications

• Experience with DRC, ERC, LVS verification and debugging
• Experience in designing custom layouts for RF high-frequency circuits such as LNAs, mixers, VCOs, and PLLs
• RF experience is advantageous

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