RFIC Layout Designer (Starshield Silicon)

United States Digital Space LLC; Hawthorne (CA); On-site; USD 105,000 - 150,000; Full time

Job summary

United States Digital Space LLC's Starshield team seeks an RFICLayoutDesigner to lead the layout discipline for advanced analog and RFIC designs, collaborating with ASIC, firmware, and verification teams to deliver high‑performance chips for space and government missions. You will design floor plans, manage parasitic minimization, perform checks, and coordinate with EDA tools, packaging, and vendors.

A bachelor in EE/CE or 3+ years' layout experience is required, with exposure to 16nm+ nodes and

Qualifications

• Bachelor’s degree or 3+ years in IC layout if no degree.
• Strong analog layout and RF layout experience required.
• Experience with 16nm, 7nm, 5nm or below preferred.

Responsibilities

• Determine chip floor plan and power/ground strategies.
• Estimate layout schedule and manage complexity.
• Perform RF/analog layout with minimized parasitics.
• Run DRC/ERC and LVS checks and fix issues.
• Integrate top-level layout with ESD structures and pad assembly.
• Collaborate with EDA vendors and guide team on techniques.

Skills

Analog layout

Advanced node layouts

RF circuit placement

LNA/VCO/Mixers layout

Scripting languages

Revision control

Linux knowledge

Communication skills

Independent problem solving

Education

Bachelor’s degree in Electrical or Computer Engineering

Tools

EDA tools

Job description

RFICLAYOUT DESIGNER(STARSHIELD SILICON)

Starshield leverages the company’s Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. As a RFICLayoutEngineer on the Starshield team, you will be working on advanced development programs in support of U.S. National Security.

We are seeking motivated, proactive, and intellectually curious engineers who will work alongside world‑class cross‑disciplinary teams (systems architecture, ASIC design, firmware, pre‑silicon verification, post‑silicon validation, product engineering, manufacturing/production, and more). In this role, you will be on a team working on multiple silicon projects that are driving more integration, lower power, mixed signal architectures and advanced silicon technology for deployment in space and ground infrastructures. You will be an integral part of the IC design team and lead the discipline of layout at the technical level and will work with RFIC/mixed signal designers on full chip layout of custom analog and RFIC designs.

RESPONSIBILITIES

• Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineers to determine pad locations
• Accurately estimate the schedule for the layout work and identify areas of complexity that need early investigation
• Perform layout of custom RF and analog circuit blocks with attention to matching and minimizing parasitic capacitance in the layout
• Perform design rule checking, electrical rule checking and layout versus schematic checks and resolve errors
• Perform top‑level layout integration with electrostatic discharge structures and pad assembly and perform final tape out (including density fill, running design for manufacturability checks and sharing GDS with the foundry)
• Work with EDA suppliers to trial new tools and features
• Generate guides and demos for others in the team to showcase improvements in layout technique

BASIC QUALIFICATIONS

• Bachelor’s degree in electrical or computer engineering or 3+ years of professional experience with integrated circuit layout design in lieu of a degree
• 1+ years of professional experience as an IC layout designer

PREFERRED SKILLS AND EXPERIENCE

• Strong analog layout skills
• Experience in advanced node IC layouts such as 16nm, 7nm, 5nm or below
• Experience in layout of circuits with frequencies up to 50GHz
• Experience in layout of sensitive RF blocks such as low noise amplifiers, voltage‑controlled oscillators and mixers
• Experience with skill programming
• Experience with shell scripting, Perl, Python or similar language
• Experience managing revision control systems
• Experience with circuit design
• Understanding of layout considerations for device matching, coupling and noise isolation
• Working knowledge of Linux
• Excellent communication skills (both oral and written) are required
• Able to work independently on challenging problems

ADDITIONAL REQUIREMENTS

• Ability to work long hours and weekends as necessary to support critical milestones
• An active clearance may provide the opportunity for you to work on sensitive company missions; if so, you will be subject to pre‑employment drug and random drug and alcohol testing

COMPENSATION AND BENEFITS

Pay Range:
Level 1: $105,000.00 - $122,500.00
Level 2: $120,000.00 - $150,000.00

Your actual level and base salary will be determined on a case‑by‑case basis and may vary based on the following considerations: job‑related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at the company. You may also be eligible for long‑term incentives, in the form of company stock or long‑term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and