RFIC Layout & Design Automation

Keysight Technologies; Calabasas (CA); On-site; USD 129,000 - 216,000; Full time

Benefits offered by this job

Medical, dental and vision

Health Savings Account

401(k) Plan

Paid Holidays

Tuition Reimbursement

ESPP (Employee Stock Purchase Plan)

Job summary

Keysight Technologies in California is seeking a highly skilled R&D Engineer to advance RFIC, analog and microwave layout and automation. You will develop parameterized layouts, layout generation, and Python-based tooling to enable design-space exploration.

Collaborate with RFIC designers and software teams to deliver production-quality automation, apply ML techniques for optimization, and integrate with circuit/EM simulations.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or a related discipline.
• Strong hands-on experience in RFIC, analog, microwave, or mixed-signal layout and design.
• Experience with RFIC passive and active components such as inductors, transformers, transmission lines, filters, matching networks, mixers, and power amplifiers.
• Deep hands-on experience in parameterized layout generation and PCell development, including automated generation of design-rule-compliant layouts from circuit and design parameters.
• Strong understanding of semiconductor layout methodologies, design rules, physical verification, parasitics, and EM-aware design practices.
• Strong programming experience in Python; C++ experience is a plus.
• Experience with circuit and/or EM simulation, design optimization, and semiconductor design automation tools.
• Strong problem-solving and software development skills with the ability to translate complex design workflows into scalable automation solutions.

Responsibilities

• Develop RFIC, analog, and microwave layouts, including parameterized and reusable layout structures.
• Develop automated parameterized layout generation capabilities that translate circuit and design parameters into design-rule-compliant physical layouts.
• Design and implement layout automation including geometry generation, placement, routing, symmetry, design-rule constraints, and EM-aware design.
• Integrate layout generation with circuit and EM simulation to support parameter exploration, design-space analysis, and optimization.
• Develop Python-based tools and scalable software for automated layout and design workflows.
• Apply optimization and machine learning techniques, including surrogate modeling and Bayesian optimization, to accelerate design exploration and convergence.
• Collaborate with RFIC designers and software engineers to deliver production-quality design automation capabilities.

Skills

RFIC layout

Python programming

C++ programming

Machine learning basics

EM/simulation tools

Education

MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD

Tools

ADS

Cadence Virtuoso

EM simulation tools

Job description

Overview

Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do.

Our award-winning culture embraces a bold vision of where technology can take us and a passion for tackling challenging problems with industry-first solutions.
We believe that when people feel a sense of belonging, they can be more creative, innovative, and thrive at all points in their careers.

We are seeking a highly skilled R&D Engineer to develop next-generation layout and design automation technologies for RFIC, analog, and microwave applications. The role is primarily focused on RFIC layout, parameterized layout generation, and layout automation, complemented by Python-based automation, simulation-driven optimization, and machine learning.

Responsibilities

• Develop RFIC, analog, and microwave layouts, including parameterized and reusable layout structures.
• Develop automated parameterized layout generation capabilities that translate circuit and design parameters into design-rule-compliant physical layouts.
• Design and implement layout automation including geometry generation, placement, routing, symmetry, design-rule constraints, and EM-aware design.
• Integrate layout generation with circuit and EM simulation to support parameter exploration, design-space analysis, and optimization.
• Develop Python-based tools and scalable software for automated layout and design workflows.
• Apply optimization and machine learning techniques, including surrogate modeling and Bayesian optimization, to accelerate design exploration and convergence.
• Collaborate with RFIC designers and software engineers to deliver production-quality design automation capabilities.

Qualifications

• MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, EDA/CAD, or a related discipline.
• Strong hands-on experience in RFIC, analog, microwave, or mixed-signal layout and design.
• Experience with RFIC passive and active components such as inductors, transformers, transmission lines, filters, matching networks, mixers, and power amplifiers.
• Deep hands-on experience in parameterized layout generation and PCell development, including automated generation of design-rule-compliant layouts from circuit and design parameters.
• Strong understanding of semiconductor layout methodologies, design rules, physical verification, parasitics, and EM-aware design practices.
• Strong programming experience in Python; C++ experience is a plus.
• Experience with circuit and/or EM simulation, design optimization, and semiconductor design automation tools.
• Strong problem-solving and software development skills with the ability to translate complex design workflows into scalable automation solutions.

Preferred Qualifications

• Experience with machine learning frameworks such as PyTorch, TensorFlow, or scikit-learn.
• Knowledge of surrogate modeling, design-space exploration, Bayesian optimization, or other optimization techniques.
• Familiarity with ADS, Cadence Virtuoso, EM simulation tools, or similar EDA platforms.
• Experience applying machine learning or intelligent optimization to semiconductor design workflows.
• Experience working in Agile software development environments.

The level of role will be based on applicable experience, education and skills; Most offers will be between the minimum and the midpoint of the Salary Range listed below.

CA pay range: MIN $129,450- MAX $215,740

Note: For other locations, pay ranges will vary by region

This role is eligible for our Keysight Results Bonus Program

US Employees may be eligible for the following benefits:

• Medical, dental and vision
• Health Savings Account
• Health Care and Dependent Care Flexible Spending Accounts
• Life, Accident, Disability insurance
• Business Travel Accident and Business Travel Health
• 401(k) Plan
• Flexible Time Off, Paid Holidays
• Paid Family Leave
• Discounts, Perks
• Tuition Reimbursement
• Adoption Assistance
• ESPP (Employee Stock Purchase Plan)
• Restricted Stock Units

Careers Privacy Statement

Keysight is an Equal Opportunity Employer

Keysight Technologies Inc. is an equal opportunity employer. Qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, protected veteran status, disability or any other protected categories under all applicable laws.