RE: 151962-1, Silicon Validation Engineer | Mountain View, CA (Hybrid) | Microsoft

ZipRecruiter; Mountain View (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

An established industry player is seeking a Silicon Verification Engineer to join their collaborative team in Mountain View. This unique role offers the chance to work on both simulation and emulation, providing valuable cross-platform verification experience. Candidates will engage in hands-on work writing and debugging tests, while also enjoying a supportive team culture led by an experienced team lead. If you have a strong background in UVM/System Verilog and a passion for verification testing, this opportunity is perfect for you to make a significant impact in a dynamic environment.

Benefits

Laptop provided

Headset provided

Wide screen monitor provided

Collaborative team environment

Qualifications

• 10+ years of experience in UVM/System Verilog verification.
• Proficient in scripting languages, especially Python.

Responsibilities

• Conduct pre-silicon verification testing on chip designs.
• Write and debug silicon verification tests.

Skills

UVM/System Verilog

Scripting (Python)

Test bench implementation

Debugging UVM tests

Verdi for debugging

Education

Bachelor's in Computer Science

Master's degree

Tools

Verdi

Job description

Job Description

Position: Silicon Verification Engineer, 151962-1.

Location: Mountain View, CA 94043 (Hybrid)

Request Summary

• Budget Approved: Yes
• Location: Hybrid Microsoft Silicon Valley Campus (SVC), California
• Onsite Requirement: 50% onsite
• Schedule: Monday-Friday, 40 hours/week (Standard business hours). No overtime. No expenses.
• Extension Opportunity: Yes
• Equipment Requirements: Supplier to provide laptop, mouse, headset, and either one wide screen monitor or two monitors.
• Attestation Required: No
• Reason for Opening: Backfill for a previous contractor
• Skill Requirements:
  • Strong expertise in UVM/System Verilog
  • Ability to implement test benches from scratch (including agents, scoreboards, checks, assertions, and cover-points)
  • Experience writing and debugging UVM tests
  • Proficiency in at least one scripting language (Python)
  • Familiarity with Verdi for source code-level debugging

Role Details

Typical Day in the Role

• Team Purpose: Pre-silicon verification testing chip designs before they reach the silicon stage.
• Key Projects: Not disclosed
• Task Breakdown:
  • 10% Meetings
  • 70% Hands-on work (writing and debugging silicon verification tests)
  • 20% Miscellaneous tasks

Why This Role Is Compelling

• Unique Opportunity: Work spans simulation and emulation, a combination rarely found even within Microsoft.
• Cross-platform verification across multiple platforms - rare and highly valuable experience.
• Team Culture: Collaborative, supportive, and experienced team. Team lead has 24 years with Microsoft.

Candidate Requirements

• Experience: Minimum 10 years of relevant industry experience
• Education:
  • Bachelor's in Computer Science, Electrical or Electronics Engineering + 7 years of UVM/System Verilog verification experience
  • OR Master's degree + 5 years of relevant verification experience
• Must-Have Skills:
  1. Minimum 10 years of UVM/System Verilog experience
  2. Minimum 10 years of experience with scripting
  3. Proven ability to write and debug tests in UVM

Indicators:

• Ability to complete work assignments independently
• Demonstrates initiative without excessive reliance on team guidance
• After a 1-month ramp-up, must show steady productivity

Interview Process

• Assessment Start: ASAP
• Assessment Format: Initial phone screen followed by a 3-4 hour panel interview
• Preparation: Candidates should be ready for live coding questions during the assessment

Contract Dates

• Start Date: April 21, 2025
• End Date: June 30, 2025