R&D Engineer Hardware 4

Broadcom; Chandler (AZ); On-site; USD 110,000 - 176,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

401K with company match

Employee Stock Purchase Program (ESPP)

Health/dental/vision insurance

Paid time off

Job summary

Broadcom is seeking a Principal Machine Learning & Silicon Yield Engineer in Chandler, AZ to predict wafer-level yield and optimize PPA from SoC telemetry and ATE test data. You will design ML, DL, and GenAI tools to translate silicon data into actionable yield and performance improvements.

Responsibilities include building predictive yield models, organizing multi-source telemetry data, interpreting circuit telemetry, and collaborating with foundry, DFM, and DFT teams to scale production.

Qualifications

• Experience predicting wafer-level yield from multi-source telemetry.
• Strong knowledge of STA and silicon telemetry.
• Proven ability to develop data-driven optimization for PPA.
• Programming skills to handle large databases.

Responsibilities

• Predictive yield modeling from large-scale telemetry data.
• Organize, clean, and analyze sensor databases.
• Interpret parametric data and on-chip sensor readouts.
• Collaborate with foundry, DFM, and DFT teams.
• Develop data workflows and scalable production release.
• Experience with spice modeling tools and Cadence Virtuoso.

Skills

Python

R

C++

ML/AI techniques

Anomaly detection

Multivariate regression

Education

MS + 6 years experience

PhD + 3 years experience

Tools

Cadence Virtuoso

Primetime STA

Spice modeling tools

Big data analysis

Job description

USA-AZ-Chandler-North Juniper Drive

Full time

R027591

Job Description:

Job Title: Principal Machine Learning & Silicon Yield Engineer

Position Overview

Broadcom is seeking a highly specialized semiconductor professional with experience in predicting wafer-level yield and optimizing PPA, from SoC telemetry and volume ATE production test data. We require deep experience in analyzing silicon architecture, static timing analysis (STA), and silicon telemetry, using advanced data analysis tools, where the goal will be to develop predictive yield and performance optimization tool sets. You will design and deploy ML, DL, and GenAI tools that translate silicon data into actionable optimized strategies.

Key Responsibilities

• Predictive Yield Modeling: Design, build, and deploy ML, DL, and GenAI models to predict and maximize wafer-level yield using large-scale SoC telemetry data.
• Telemetry Data: Organize, clean, and analyze large, multi-source sensor databases and provide input on future telemetry requirements.
• Circuit Telemetry & Silicon Expertise: Interpret complex parametric data, on-chip sensor readouts, and circuit telemetry to isolate failure mechanisms and marginalities.
• Cross-Functional Collaboration: Partner with foundry, product engineering, design-for-manufacturing (DFM), DFT engineering teams to drive yield and PPA strategies.
• Innovate, Scale, Deploy: Develop, qualify and productize experimental data workflows, and work with teams to release to scalable production.
• S pice modeling and simulation: Must have experience in spice modeling tools, Cadence Virtuoso and familiarity with Primetime STA tools.

Required Qualifications

• Education: MS plus 6 years experience OR Ph.D. plus 3 years experience in Electrical Engineering, Computer Science or a related field Top-tier semiconductor research institution, e.g. Stanford, UC Berkeley, MIT, Purdue, UIUC preferred.
• Yield & Telemetry Experience: Proven track record in the semiconductor industry specializing in silicon macro characterization and SoC telemetry analysis.
• Advanced Analytics: Deep expertise in applying Machine Learning and Artificial Intelligence techniques (e.g., deep learning, anomaly detection, multivariate regression) to physical hardware datasets.
• Data Engineering Skills: Strong programming skills in Python, R, or C++ and hands‑on experience handling massive databases.
• Domain Knowledge: Deep understanding of semiconductor manufacturing processes, wafer fabrication, DFM practices, and electronic design automation (EDA tools).

Compensation and Benefits

The annual base salary range for this position is USD 109,700.00 To USD 175,500.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Welcome! Thank you for your interest in Broadcom!

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