R&D Engineer Adv Tech Dev 1

Broadcom; San Jose (CA); On-site; USD 66,000 - 105,000; Full time

Job summary

A leading technology company is seeking a talented individual to join their IC packaging team. The role involves working on advanced node silicon chip designs, collaborating with various engineering teams, and ensuring high-quality package solutions. Ideal candidates will have a strong educational background in engineering and a deep understanding of signal and power integrity concepts. This position offers competitive compensation and comprehensive benefits, including medical, dental, and equity awards.

Benefits

Medical Insurance

Dental Insurance

Vision Insurance

401(k) with company match

Employee Stock Purchase Program

Paid Holidays

Sick Leave

Vacation

Qualifications

• 0-2+ years in IC packaging and assembly; exceptional fresh graduates considered.
• Deep understanding of signal integrity and power integrity concepts.

Responsibilities

• Work with chip design team for new advanced node silicon chip floor plan.
• Manage IC packaging activities from concept through development and production.
• Collaborate with teams to select optimal package solutions based on requirements.

Skills

Signal Integrity

Power Integrity

Project Management

Communication

Leadership

Education

BS/MS/PhD in Material Science

BS/MS/PhD in Electrical Engineering

BS/MS/PhD in Mechanical Engineering

Tools

Cadence APD

Job description

Please Note:

1. If you are a first-time user, please create your candidate login account before applying for a job. (Click Sign In > Create Account)

2. If you already have a Candidate Account, please Sign-In before you apply.

Job Description:

• Work with Business Units chip design team & Analog / Digital IP owners (e.g., 224 PAM*, 112G PAM4, HBM2e/3) for new advanced node silicon (7nm, 5nm, 3nm...) chip floor plan & IP bump pattern design and optimization for package design requirements (e.g., layer-count, stack-up, escape architecture, BGA pattern development, s-parameter extraction/comprehension and optimization [RL, NEXT/FEXT, IL etc.], and power integrity [PI] requirements).
• Collaborate with business unit marketing and IC design teams to select the optimal package solution based on cost, performance, manufacturability, and reliability for new advanced silicon node products.
• Work with IC design, system design, package SI/PI & thermal engineering teams to design custom packages.
• Ensure designed packages meet CPI, SI/PI, and thermal requirements (1000W+) of advanced node silicon products.
• Research, develop, and productize new materials such as TIM, build-up-film, underfill, etc., supporting advanced node silicon (7nm & 5nm) POR definition.
• Manage IC packaging activities from concept through development, qualification, and high-volume production.
• Define assembly BOM, processes, troubleshoot, and support packaging issues on new advanced technology.
• Implement, fine-tune, and productize new technologies into high-volume manufacturing (HVM).
• Create package design documentation and assembly instructions.
• Work closely with QA and customers to resolve quality issues.
• Interface with packaging assembly and substrate suppliers for new product bring-up, qualification, and ramp-up.
• Coordinate with other operational groups such as product engineering, foundry, test, and QA.
• Participate in package technology development and productivity projects (e.g., assembly process enhancement, new TIM material development).
• Interface with external tier #1 customers for custom ASIC programs or support for development, quality, and issue resolution.

Job Requirements:

• BS/MS/PhD in Material Science, Electrical, or Mechanical Engineering.
• Experience: 0-2+ years in IC packaging and assembly; exceptional fresh graduates will be considered.
• Deep understanding of signal integrity and power integrity concepts such as characteristic impedance, s-parameters (RL, IL, FEXT/NEXT, etc.), power plane impedance, and optimization.
• Proficiency in Cadence APD for custom substrate design.
• Hands-on experience with advanced assembly processes for flip-chip, MCM packages, and 2.5D packaging for advanced nodes (7nm, 5nm, beyond).
• Good understanding of materials related to Chip Packaging Interaction (CPI).
• Familiarity with wafer BEOL processes related to CPI (top metal, passivation, UBM, bumping, etc.).
• Knowledge of advanced substrate manufacturing processes (e.g., SAP/mSAP, PSPI with Cu RDL).
• In-depth knowledge of failure analysis techniques on advanced node silicon products (7nm, 5nm, etc.) with ELK and MiM structures.
• Conceptual understanding of package cost structure.
• Strong project management, communication, and leadership skills.
• Ability to read and understand mechanical drawings, with knowledge of GD&T.
• Understanding of manufacturing and quality engineering fundamentals (DOE, process capability indices, etc.).
• The role requires versatility; candidates should be able to grow across multiple disciplines, including manufacturing, quality, materials, electrical, thermal, and mechanical.
• A record of innovation, such as journal publications or patents, is a plus.
• Familiarity with advanced technologies like 2.5D, 3D patterned structures, inductors in package substrates, and substrate technology is advantageous.

Additional Job Details:

Compensation and Benefits:

The annual base salary range is $66,000 - $105,000.

Eligible for a discretionary annual bonus, equity awards, and a comprehensive benefits package including medical, dental, vision, 401(k) with company match, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), paid holidays, sick leave, and vacation. The company complies with applicable laws regarding paid family leave and other leaves of absence.

Broadcom is an equal opportunity employer. We consider all qualified applicants regardless of race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability, medical condition, pregnancy, veteran status, or other protected characteristics. We also consider qualified applicants with arrest and conviction records consistent with local laws.

If you are outside the USA, please include your home address for future correspondence.