R&D Engineer Adv Tech Dev 1

Broadcom; Irvine (CA); On-site; USD 66,000 - 105,000; Full time

Job summary

A leading company in semiconductor manufacturing is seeking an R&D Engineer to focus on advanced chip packaging technologies. This role involves collaborating with various engineering teams to optimize package designs and ensure they meet performance and reliability standards. Candidates should have a strong educational background in engineering and a keen understanding of signal integrity concepts. The position offers a competitive salary and comprehensive benefits.

Benefits

Health Plans

401(k)

ESPP

Paid Holidays

Leaves

Qualifications

• 0-2+ years of experience in IC packaging and assembly; exceptional fresh graduates considered.
• Strong understanding of signal and power integrity concepts.

Responsibilities

• Collaborate with chip design teams for advanced node silicon chip floor planning.
• Manage IC packaging activities from concept to high-volume production.
• Research and implement new materials for advanced node silicon.

Skills

Project Management

Communication

Leadership

Education

BS/MS/PhD in Material Science

BS/MS/PhD in Electrical Engineering

BS/MS/PhD in Mechanical Engineering

Tools

Cadence APD

Job description

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Responsibilities

1. Collaborate with Business Units chip design team & Analog / Digital IP owners (e.g., 224 PAM*, 112G PAM4, HBM2e/3) for advanced node silicon (7nm, 5nm, 3nm) chip floor planning & IP bump pattern design, optimizing for package design requirements such as layer count, stack-up, escape architecture, BGA pattern, s-parameter extraction and optimization (RL, NEXT/FEXT, IL), and power integrity.
2. Coordinate with marketing and IC design teams to select optimal package solutions balancing cost, performance, manufacturability, and reliability for cutting-edge silicon nodes.
3. Work with IC design, system design, package SI/PI, and thermal engineering teams to develop custom packages.
4. Ensure packages meet CPI, SI/PI, and thermal requirements (>1000W) for advanced silicon products.
5. Research, develop, and implement new materials (e.g., TIM, build-up films, underfill) supporting advanced node silicon (7nm & 5nm).
6. Manage IC packaging activities from concept to high-volume production, including defining BOMs, processes, troubleshooting, and supporting packaging issues.
7. Implement and refine new technologies into high-volume manufacturing (HVM).
8. Create detailed package design documentation and assembly instructions.
9. Collaborate with QA and customers to resolve quality issues.
10. Coordinate with suppliers for product bring-up, qualification, and ramp-up.
11. Engage with other operational groups such as product engineering, foundry, test, and QA.
12. Participate in technology development and productivity projects, e.g., process enhancements and new material development.
13. Interface with external customers for custom ASIC programs and development support.

Job Requirements

• BS/MS/PHD in Material Science, Electrical, or Mechanical Engineering.
• 0-2+ years of experience in IC packaging and assembly; exceptional fresh graduates considered.
• Strong understanding of signal and power integrity concepts (characteristic impedance, s-parameters, power plane impedance).
• Proficiency in Cadence APD for custom substrate design.
• Hands-on experience with advanced assembly processes (flip-chip, MCM, 2.5D).
• Solid knowledge of CPI-related materials and wafer BEOL processes.
• Familiarity with advanced substrate manufacturing (SAP/mSAP, PSPI, Cu RDL).
• Experience with failure analysis techniques on advanced node silicon (ELK, MiM).
• Understanding of package cost structures.
• Strong project management, communication, and leadership skills.
• Ability to read mechanical drawings and knowledge of GD&T.
• Fundamentals of manufacturing and quality engineering (DOE, process capability).
• Ability to grow across multiple disciplines: manufacturing, materials, electrical, thermal, mechanical.
• Innovation record via publications or patents is a plus.
• Knowledge of advanced technologies like 2.5D/3D structures is advantageous.

Additional Information

The annual salary range is $66,000 - $105,000, with eligibility for bonuses and equity.

Broadcom offers comprehensive benefits including health plans, 401(k), ESPP, paid holidays, and leaves.

Job Details

• Seniority level: Mid-Senior level
• Employment type: Full-time
• Industry: Semiconductor Manufacturing