Quantum Qubit Design Engineer

Intel Corporation; Hillsboro (OR); On-site; USD 142,000 - 269,000; Full time

Job summary

Intel Corporation, located in Hillsboro, Oregon, is building a world-class quantum computing team focused on silicon-based qubits and scalable processors. This role, within the Quantum Computing Group, targets design, tapeout, and system integration of qubit devices across the full silicon stack.

You will collaborate with lithography, process integration, measurement, TCAD, and software teams to enable large-scale quantum processors, while ensuring reliable performance and manufacturability in a

Qualifications

• Bachelor's degree with 4 years of experience, Master's with 3 years, or Ph.D. in Physics, Electrical/Cryogenic/Quantum Engineering or related field.
• Experience with EM modeling, cell design, design automation and PDK-related flows.
• Experience scripting or configuring APR tools (e.g., TCL) and running standard validations.

Responsibilities

• Establish qubit processes and design rules with lithography and PDK teams.
• Architect qubit/readout cell design and automation, enabling scaling to millions of qubits.
• Collaborate with TCAD, PDK, and tool vendors to create qubit process models and extraction capability.
• Support quantum software and control teams in tradeoff analyses for error correction and topology.
• Develop automated place-and-route flows for large-scale quantum processors.
• Create signal integrity strategies and bespoke PDKs for high-density interconnects.
• Taping out qubit processors from PDK implementation through Fab NPI and tapeout states.

Skills

EM modeling

Standard cell design

Design automation

APR routing

PDK experience

TCL scripting

VSR/MSOA tooling

Education

Bachelor/Master/PhD in Physics or Electrical/Quantum Eng

Tools

EDA tools

Python programming

Job description

Job Details: Job Description:

Intel Corporation is the world's largest semiconductor company and a global leader in computing innovation. Our Quantum Computing Group represents Intel's bold venture into the next frontier of computing technology, leveraging our decades of semiconductor manufacturing expertise to develop silicon-based quantum processors. We're pioneering spin qubit technology in silicon quantum dots, combining cutting-edge quantum physics with Intel's unmatched manufacturing capabilities to create the world's first commercially viable quantum computers. Our collaborative approach spans the entire quantum compute stack while harnessing the power of Intel's 18A process and design infrastructure. We are seeking an exceptional Quantum Design Engineer to join our pioneering quantum computing team. In this position, you will be joining a team of incredibly talented engineers focused on the challenging task of scaling our quantum computing chips to millions of qubits. Here you will be involved in all aspects of the qubit chip process from initial conception through Process-Design-Kit definition, design execution and tapeout, along with ensuring silicon runs smoothly in fab and final system integration. You'll work closely not only with our qubit, control, system integration, and software/algorithms teams, but also with teams in Foundry lithography, process and design. You'll be working at the intersection of cutting-edge semiconductor technology and quantum physics, creating solutions that push the boundaries of what's possible in computing.

Ready to help build the future of quantum computing? Be part of this extraordinary journey.

Join Intel's Quantum Computing Group and be part of a team that's not just researching quantum computing - we're building it. If you're passionate about combining cutting-edge quantum physics with real-world applications and want to work with the resources and expertise of the world's leading semiconductor company, we want to hear from you.

Key Responsibilities

• Work alongside lithography, process integration, measurement, and PDK engineers to establish qubit processes and design rules
• Architect qubit and readout element standard cell design and automation
• Engage with TCAD and PDK engineers and design tool vendors to create qubit and read-out universal process files and qubit level models and extraction capability
• Partnering with quantum software and control engineers to analyze tradeoffs on quantum error correction schemes vs qubit topology
• Design automation to enable front end design automation and routing generation for enabling routing of large scale quantum processors
• Creation of Automated Place and Route flows to enable qubit routing, including AI and machine-based learning routing optimization for large I/O counts
• Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable routing of large-scale quantum processors
• Drive signal integrity analysis to define routing strategies for large scale qubit processors and work to define and release customized PDKs
• Perform signal integrity analysis and optimization for qubit processors to ensure optimal performance for signal integrity and crosstalk
• Working with PDK engineers and design tool vendors to create new signal extraction capability for large scale quantum processors
• Work in a collaborative team to execute design of qubit processors from PDK implementation through Tapeout and Fab NPI
• Perform industry standard design validations such as DRC, LVS, and Extraction prior to tapein signoff
• Work closely with Control, Packaging and System teams to co-design Interposer interfaces and routing strategies for bridging the Qubit processor to ASIC control
• Designing and taping out electrical characterization test structures to characterize qubit and interconnect performance and yield
• Working with PDK engineers and design tool vendors to create new customized EDA tool capability to enable thermal analysis of large scale quantum processors
• Implement PDK collateral into customized design environments and create and maintain customized design workflows for qubit processors
• Working with external customers to understand their needs and provide solutions based on Intel's quantum PDK
• Ensure successful implementation of Intel quantum PDK design collateral and EDA tool capabilities for External Customers
• Ensuring external customer designs are successfully taped out with silcon run to end-of-line on schedule

As a successful candidate, you must possess

• Excellent communication and presentation skills for technical and non-technical audiences
• Keen experimental insight with the ability to design and focus on practical implementations
• High motivation and enthusiasm for self-directed, hands‑on work
• Creativity and flexibility to thrive under changing priorities and evolving program needs
• Strong analytical thinking and problem‑solving capabilities
• Collaborative mindset with ability to work effectively across diverse teams
• Adaptability to work in a fast‑paced, innovative environment
• Leadership potential to drive independent R+D initiatives
• Passion for pushing the boundaries of quantum technology development

Minimum Qualifications

• Bachelor's degree with 4 years of experience, Master's degree with 3 years of experience, or Ph.D. degree in Physics, Electrical Engineering, Cryogenic Engineering, Quantum Technologies, or Quantum Engineering or related Engineering field
• Must possess 1+ years experience with at least one of the following: o Electromagnetic (EM) modeling and simulation tools and their application to signal integrity/crosstalk analysis for high-speed/high-density on-chip/on-package interconnect o Standard cell design, design automation flow implementation (SKILL, VSR, MSOA or equivalent), and universal process file models and extraction o Digital design tools and APR based routing design and ability to script and configure APR tools with languages such as TCL o Designing and taping out designs on a mainstream foundry process PDK including running all industry standard validations such as DRC, ERC, LVS, PEX. o Implementing PDK collateral and design flows to enable and maintain design environments

Preferred Qualifications

• 1+ years of experience with: o Electrical measurement experience with qubit, quantum devices, transistors, or integrated circuits o Process-Integration experience with qubit or CMOS devices or interconnects o Experience with dilution refrigerators or other cryogenic systems o RFIC design or experience with cryogenic control of qubits o Design of superconducting circuits and superconducting interconnects o Programming, software, or driver development and scripting for task automation using languages such as Python o Implementing Machine Learning or AI based digital design routing algorithms o Working with EDA tool vendors to enable customized design solutions

Benefits at Intel

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Job Type: Experienced Hire Shift: Shift 1 (United States of America)

Primary Location: US, Oregon, Hillsboro

Additional Locations: US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, New York, New York, US, Pennsylvania, Allentown, US, Texas, Austin

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust: N/A

Work Model for this Role This role will require an on-site presence.

* Job posting details (such as work model, location or time type) are subject to change.

* ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.