Product Operations Engineer

DensityAI, Inc.; Mountain View (CA); On-site; USD 200,000 - 285,000; Full time

Job summary

DensityAI, Inc. seeks a Product Engineer / Product Operations Engineer to bridge design, test, manufacturing, and customers, helping stand up the product-engineering / product-operations function from the ground up.

You will own products from first silicon through qualification, ramp, and sustaining to drive yield, test quality, cost, and supply. You will partner with DFT, design, and test teams, establish foundry/OSAT relationships, manage NPI and ramp, and lead data-driven improvements across

Qualifications

• Bachelor's or Master's in Electrical Engineering, Materials/Semiconductor Engineering, or related field.
• Hands-on experience in semiconductor product engineering, test engineering, or operations for complex digital/SoC/ASIC products.
• Strong understanding of the semiconductor manufacturing flow—wafer fab, wafer sort, assembly, and final test.

Responsibilities

• Own assigned products across the full lifecycle: NPI, characterization, qualification, ramp, and sustaining.
• Drive yield analysis and improvement—monitor wafer sort and final test yield, lead failure analysis and root-cause efforts.
• Own the multi-die yield story—KGD sorting, die-to-package matching and binning, yield across assembly/packaging.
• Manage test program quality and optimization across wafer sort, final test, and SLT; drive test time reduction and cost trade-offs.
• Lead silicon characterization across PVT corners; define specs, shmoo analysis, datasheet correlation.
• Own product qualification (HTOL, HAST, TC, ESD) and reliability sign-off per JEDEC standards.
• Establish and drive production operations: lot disposition, capacity and WIP, binning/grading; coordinate with foundry/OSAT.
• Monitor production data—SPC, yield dashboards, and statistical analysis to detect excursions and drive CAPA.
• Lead 8D/CAPA, containment, root-cause, and RMA handling; drive cost-reduction initiatives.

Skills

Yield analysis

NPI

KGD / multi-die

SPC / data analysis

JMP

Python

DFT / test concepts

Education

Electrical Engineering

Materials/Semiconductor Engineering

Tools

JMP

Python

Advantest

Teradyne

Job description

We are seeking a Product Engineer / Product Operations Engineer to serve as the critical link between design, test, manufacturing, and the customer, and to help stand up the product-engineering / product-operations function from the ground up. In this role you will own products from first silicon through qualification, ramp, and sustaining—driving yield, test quality, cost, and supply to ensure our multi-die devices ship on time, at the volumes datacenter silicon demands, and at target margin. You will partner with DFT, design, and test engineering, and help establish the foundry/OSAT and operations relationships needed to take products from bring-up through ramp and sustaining for advanced-packaging datacenter silicon.

What you'll do

Own assigned products across the full lifecycle: new product introduction (NPI), characterization, qualification, ramp, and sustaining

Drive yield analysis and improvement—monitor wafer sort and final test yield, lead failure analysis and root-cause efforts, and partner with design/test to closegaps

Own the multi-die yield story—known-good-die (KGD) sorting, die-matching and binning across a package, assembly and packaging yield, and cost-per-package risk (a single marginal die can sink an entire multi-die assembly)

Manage test program quality and optimization across wafer sort, final test, and system-level test (SLT)—test time reduction, coverage vs. cost trade-offs, guardbands, and outlier/screening strategies (PAT/SBL/SYL) used to screen marginal die for KGD

Lead silicon characterization across PVT corners; define spec limits, shmoo analysis, and datasheet correlation

Own product qualification (HTOL, HAST, TC, ESD/latch-up, etc.) and reliability sign-off in line with JEDEC standards as applicable

Establish and drive production operations: lot dispositioning, capacity and WIP management, binning/grading strategy, and coordination with foundry and OSAT (assembly/test) partners

Monitor and act on production data—SPC, yield dashboards, and statistical analysis (JMP/Python) to detect excursions and drive corrective action

Lead excursion management and 8D/CAPA—contain, root-cause, and resolve manufacturing and quality issues; establish customer-return (RMA/FA) handling

Drive cost reduction and continuous improvement—test time, yield, package, and material cost initiatives

Helpestablish customer-quality processes—field issue resolution, quality reporting, and audits

What we're looking for:

Bachelor's or Master's in Electrical Engineering, Materials/Semiconductor Engineering, or related field

Hands‑on experience in semiconductor product engineering, test engineering, or operations for complex digital/SoC/ASIC products

Strong understanding of the semiconductor manufacturing flow—wafer fab, wafer sort, assembly, and final test

Multi‑die / advanced‑package product engineering—known‑good‑die (KGD) sorting, die‑to‑package matching and binning, assembly and packaging yield, and cost‑per‑package management

Experience with foundry and OSAT relationships and offshore test/assembly operations

Experience with ATE platforms (Advantest, Teradyne) and test program development, debug, and optimization, including system‑level test (SLT)

Solid grounding in yield analysis, statistics, and data analysis—SPC, distributions, correlation; proficiency with JMP, Python, or equivalent

Experience with silicon characterization (PVT corners, shmoo, spec setting) and datasheet correlation

Working knowledge of product qualification and reliability methodologies (JEDEC).

Familiarity with DFT/test concepts—scan, MBIST, ATPG patterns, boundary scan—and how they map to production test

Knowledge of outlier screening methods (PAT/SBL/SYL) applied to known‑good‑die (KGD) screening—identifying marginal die before they are committed to an expensive multi‑die package

Experience with NPI program management and product ramp/sustaining for advanced‑packaging datacenter silicon

Familiarity with multi‑die package technologies and assembly processes.

Structured problem‑solving / continuous‑improvement methodology (8D, CAPA, DOE, or equivalent)

Strong cross‑functional collaboration skills and the ability to drive issues to closure across design, test, fab, and OSAT partners

Compensation

Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.

$200,000 - $285,000 USD

Export Controls

Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.

DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in DensityAI’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.

A "recently separated veteran" means any veteran during the three‑year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.