Product Development Engineer, GPU/ASIC — Drive Silicon to Market

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 136,000 - 259,000; Full time

Job summary

NVIDIA in Santa Clara, California is seeking Product Development Engineers to turn NVIDIA's chips into consumer, professional and data center products. You will work on productizing GPUs, driving architecture to market, and partnering across teams.

You will lead DOE-based solutions, improve test times, analyze test data with JMP, and influence ASIC designs. Applicants should have 5+ years of relevant experience and a degree in Electrical Engineering.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering or equivalent.
• 5+ years of product development engineering or relevant experience.
• Strong problem solving, data-driven decisions, and critical thinking.
• Experience with digital design, circuit analysis, characterization and qualification.

Responsibilities

• Drive latest architecture designs to market as part of the product engineering team.
• Pioneer ATE test methodologies for next-generation GPU circuits and silicon assembly.
• Identify and resolve yield bottlenecks and analyze test failures at wafer and package levels.
• Propose DOEs and develop solutions to complex characterization problems.
• Lead cross-functional efforts with foundry, DFT, test, planning and quality to root-cause issues.
• Influence next-generation ASIC designs to improve circuit quality and testability.

Skills

Attention to detail

Data-driven decision making

Critical thinking

Problem solving

Cross-functional collaboration

Education

Bachelor's or Master's degree in Electrical Engineering or equivalent

Tools

ATE test flows

DFT

Device physics

Statistical data analysis (JMP)

Job description

NVIDIA in Santa Clara, California is seeking Product Development Engineers to turn NVIDIA's chips into consumer, professional and data center products. You will work on productizing GPUs, driving architecture to market, and partnering across teams.

You will lead DOE-based solutions, improve test times, analyze test data with JMP, and influence ASIC designs. Applicants should have 5+ years of relevant experience and a degree in Electrical Engineering.