Process Integration Development Engineer - Defect Metrology

Intel Corporation; Hillsboro (OR); Hybrid; USD 99,000 - 140,000; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health, retirement, and vacation

Job summary

Intel Corporation in Hillsboro, Oregon, seeks a Defect Metrology Engineer for the LTD Defect Metrology group. You will identify defects impacting yield in advanced silicon processes and develop root-cause fixes using MBPS and 8D methods.

This role blends hands-on metrology with cross-functional collaboration to ensure Best-in-Class targets and high-quality yields. We value strong data analysis, problem-solving, and communication skills; you will lead defect reviews, drive improvement roadmaps,

Qualifications

• Master's degree in a relevant engineering/science field.
• Hands-on experimental research experience and data analysis.
• Excellent communication and cross-functional collaboration.

Responsibilities

• Own a process segment to ensure metrology detects yield-limiting defects.
• Investigate baseline shifts to restore defect health to capable baseline.
• Develop new recipes and RFCs for New Product Introduction.
• Lead with metrology tools and test vehicles to meet yield objectives.
• Present defect summaries to LTD, MDCE, and engineering teams.
• Partner with Integration, Yield and Failure Analysis labs for root causes.
• Ensure quality through IMT and FT forums and drive improvement.
• Collaborate across LTD Defect metrology group to sustain excellence.

Skills

Data analysis

Problem solving

Communication

Team collaboration

Education

Master's degree in Materials Science and Engineering; Electrical/Chemical/Mechanical Engineering; Physics; Nuclear Engineering; Optics; Chemistry; CS

Tools

MATLAB

Excel

JMP

Python

Job description

Embark with us on a journey of growth and transformation as we create exceptionally engineered technology and bring AI everywhere. As a valued team member, your adaptability and attention to detail will contribute to our drive for results and relentless pursuit of quality, ensuring we meet our customers' needs with precision. Join us and build on our legacy of innovation and collaboration as we deliver world‑changing technology that improves the life of every person on the planet. Life at Intel: https://jobs.intel.com/en/life-at-intel

At Intel's Logic Technology Development (LTD), we have continued to extend Moore's law to be world leaders in computing technology. To achieve the necessary scaling of our semiconductor manufacturing process, we have led the industry in developing enhancements such as strained silicon for carrier transport enhancement, high-k metal gates, FinFETs, and next-generation Gate-All-Around architectures. LTD has been at the center of every new development that has kept Moore's Law moving forward.

Defect Metrology plays a key role in the development of every new silicon process technology. Our analysis builds the plan that allows LTD to take technology from the research phase to the high-volume manufacturing phase while maintaining high-quality standards.

In the Manufacturing Integration Engineering (MIE) organization, we engineer world‑class yields on advanced processes by driving defects down to Best‑in‑Class targets. As a Defect Metrology Engineer, you will be responsible for identifying all defects that impact yield and performance in an advanced silicon process technology. You will characterize the process using cutting‑edge metrology tools. With this characterization, you will be responsible for investigating the root cause owners and developing defect reduction roadmaps to achieve program milestone commitments to our customers. You will then work directly with the process modules and integration teams to drive that roadmap by developing and qualifying process fixes through Model‑Based Problem Solving (MBPS). You will also respond to defect baseline shifts to isolate the root cause and implement preventative actions consistent with 8D methodology. This role provides an opportunity to influence Intel's future process technologies that will keep Moore's Law moving forward.

Responsibilities

• Owning a segment of the process to ensure adequate metrology is placed to detect and respond to all yield‑limiting defects prior to reaching end‑of‑line sort.
• Investigate and respond to exclusionary baseline shifts to ensure segment defect health is restored to capable, demonstrated baseline.
• Develop new recipes and RFCs as part of New Product Introduction (NPI).
• Provide navigation and leadership to meet Intel's yield objectives, utilizing state‑of‑the‑art metrology tools and test vehicles (QTM, Short Loop, etc.).
• Organizing and presenting defect summaries to F25, LTD, MDCE engineering teams.
• Partnering with Intel Integration, Yield, and failure analysis labs to provide root cause for all defect issues.
• Hold the team and collaborators accountable for quality through Integrated Module Team (IMT) and Focus Team (FT) forums.
• Work collaboratively as a part of the overall LTD Defect metrology group.
• Role‑model and establish a team culture of trust, collaboration, safety, accountability, and sustaining excellence.
• Build strong relationships with other LTD teams based on mutual trust and respect.

Ideal Candidate Must Demonstrate

Strong data analysis and problem debug skills. Team player with flexibility and adaptability to changing business needs. Strong ownership mindset and driving closure‑see the problem, own the problem. Excellent communication and navigation skills to larger audiences. Understand and adhere to Intel cultural values such as Customer First, Fearless Innovation, Results Driven, One Intel, Integrity, Quality, Inclusion.

Qualifications

Minimum qualifications:

• Must possess a Master's degree in Materials Science and Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Nuclear Engineering, Optics, Chemistry, or Computer Science.
• Hands‑on experimental research experience: designing and conducting experiments, operating laboratory equipment (characterization, fabrication, or synthesis), and analyzing statistical data.

Preferred qualifications:

• Demonstrated academic research, coursework, laboratory, or internship experience with one or more of the following: Materials characterization (SEM, TEM, AFM, etc.), materials fabrication, synthesis, metrology, statistical or data analysis (MATLAB, Excel, JMP, Python, etc.).
• Semiconductor processing fundamentals (lithography, wet and/or dry etch, chemical mechanical polishing, thin films), semiconductor and/or transistor device physics, and Design of Experiments (DOE).
• Defect metrology, defect inspection/improvement, yield analysis, or process integration.
• Demonstrated application of Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
• Complex problem‑solving methodologies: root cause analysis, Model‑Based Problem Solving (MBPS), 5 Why, Fishbone diagrams, or 8D frameworks.
• Understanding of semiconductor physics or semiconductor processing cleanroom unit operations.
• Understanding of defect metrology tools such as brightfield, darkfield, or voltage contrast (VC).

We welcome motivated professionals to bring their expertise and enthusiasm to Intel, where you will have the opportunity to grow your career while helping to shape the future of technology in a collaborative and forward‑thinking environment.

Benefits

• Competitive pay
• Stock bonuses
• Benefit programs which include health, retirement, and vacation.

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $99,030.00-139,810.00 USD

Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Job Type

College Grad

Shift

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Work Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. * Job posting details (such as work model, location or time type) are subject to change.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

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