Principal Systems Engineer, RELIC Compute Architecture

Rune; Mountain View (CA); Hybrid; USD 320,000 - 520,000; Full time

Benefits offered by this job

Hybrid work schedule

Job summary

Rune in Mountain View, CA is seeking a Senior compute architect to own the RELIC hardware stack—from node composition to fabric and the serving stack. You will define the technical direction for GPUs, CPUs, NICs and DPUs, and partner with the CTO to shape two hardware generations in a hybrid office setting.

This is a systems role, not a component role: you’ll reason from workloads to scale-up domains, scale-out fabrics and power envelopes, map performance targets and cost per token, and lead

Qualifications

• 10+ years of systems architecture for AI/HPC or hyperscale compute.
• Ability to explain when a workload needs large NVLink domains vs. tuned RDMA fabrics.
• Experience with NVLink/NVSwitch, InfiniBand and RoCEv2, plus familiarity with UALink/Ultra Ethernet.

Responsibilities

• Define the next-gen RELIC compute platform across accelerators, CPUs, NICs, and DPUs.
• Architect scale-up domains (NVLink/NVSwitch) and scale-out fabrics (topology, RoCEv2, optics).
• Co-design inference stack with hardware and software (SGLang, vLLM, TensorRT-LLM, Dynamo).
• Build performance and TCO models using measured data from clusters.
• Lead vendor engagements and drive platform bring-up and validation.

Skills

AI/HPC systems architecture

Cross-disciplinary problem solving

Hands-on cluster experience

Tools

NVLink/NVSwitch

InfiniBand

RoCEv2

NVIDIA CUDA ecosystem

Job description

The role

You will own the compute architecture of next-generation RELIC: what goes in the node, how nodes connect, and how the serving stack maps onto both. Reporting to the CTO, you set the technical direction for every GPU, CPU, NIC, switch and fabric decision we make over the next two hardware generations.

You will own the compute architecture of next-generation RELIC: what goes in the node, how nodes connect, and how the serving stack maps onto both. Reporting to the CTO, you set the technical direction for every GPU, CPU, NIC, switch and fabric decision we make over the next two hardware generations. This is a systems role, not a component role. You will reason from model and workload characteristics down to the scale-up domain, the scale-out fabric, memory hierarchy and power envelope, then back up to tokens per second per megawatt and cost per million tokens. This role is based in our Mountain View, CA. We work hybrid and you’d be in the office three days a week.

What You'll Do

• Define the next-gen RELIC compute platform. Evaluate and select accelerators, host CPUs, NICs and DPUs across NVIDIA (Blackwell Ultra, Rubin), AMD (MI3xx/MI4xx) and emerging inference silicon. Make the call on HGX-class nodes versus rack-scale NVL systems for each site.
• Architect the scale-up domain. Size NVLink/NVSwitch domains and partitioning (e.g. NVL72-class racks), and track open alternatives such as UALink and Ethernet-based scale-up. Decide what domain size each workload actually needs.
• Architect the scale-out and front-end fabrics. Own topology (rail-optimized, fat-tree, multi-plane), RoCEv2 congestion control, Ultra Ethernet readiness, optics and transceiver strategy, and storage and KV-cache networks.
• Co-design the inference stack with the hardware. Map disaggregated prefill/decode, KV-cache transfer and offload, MoE expert parallelism, tensor/pipeline parallelism and speculative decoding onto the platform. Work hands-on with SGLang, vLLM, TensorRT-LLM and NVIDIA Dynamo.
• Build the models that drive decisions. Own performance, roofline and TCO models covering throughput, latency SLOs, perf/W, $/token and tokens/s/MW, and keep them honest against measured data from our clusters.
• Own the roadmap and vendor technical relationships. Lead deep-dives with NVIDIA, AMD, OEMs and network vendors; influence early-access programs; write the architecture specs that procurement and site teams build to.
• Stay close to the metal. Lead bring-up and validation of new platforms and drive root cause on fabric, NIC and node-level issues when they block production.

What You Bring

• 10+ years in systems architecture for AI, HPC or hyperscale compute, including at least one platform you took from paper to production at cluster scale.
• Scale-up vs. scale-out, deeply. You can explain when a workload needs a large NVLink domain versus a well-tuned RDMA fabric, and quantify the cost of getting it wrong. Hands-on with NVLink/NVSwitch, InfiniBand and RoCEv2 (PFC, ECN, DCQCN), and familiar with UALink and Ultra Ethernet.
• GPU architecture fluency. SM and tensor-core design, HBM capacity and bandwidth, low-precision formats (FP8, FP4/MXFP4), and how each shows up in prefill versus decode.
• CPU and host architecture. Arm and x86 server cores (e.g. Grace, Neoverse, EPYC, Xeon), NUMA, PCIe Gen5/Gen6, CXL, and the host's role in data movement and KV-cache tiering.
• Modern inference software. Working knowledge of disaggregated serving, continuous batching, paged attention, KV-cache reuse and transfer, and MoE parallelism, with hands-on time in at least one of SGLang, vLLM, TensorRT-LLM or Dynamo.
• Quantitative modeling. You build performance and TCO models from first principles and defend them with benchmarks.
• Embedded in the AI/HPC community. You follow and contribute to the ecosystem: papers, open-source projects, OCP or MLPerf work, conference talks, or deep vendor relationships.
• Builder's temperament. Comfortable owning ambiguous, cross-disciplinary problems at an early-stage company and getting hands dirty in a cluster when needed.

Nice to have

• Silicon or microarchitecture background (CPU, GPU, NPU or network ASIC design or performance architecture).
• Experience with rack-scale systems: liquid cooling, busbar or DC power distribution, 800G/1.6T optics.
• Familiarity with power electronics, DC-coupled architectures, or behind-the-meter power.
• Collective-communication work (NCCL, RCCL, NVSHMEM, NIXL) or HPC experience with MPI-scale jobs.
• Contributions to SGLang, vLLM, Dynamo, LMCache or similar serving projects.
• Experience evaluating non-GPU inference accelerators and building the business case for or against them.
• Published papers or patents in computer architecture, networking or ML systems.