Principal Systems Engineer, RELIC Compute Architecture

Rune; Mountain View (CA); Hybrid; USD 260,000 - 360,000; Full time

Job summary

Polymer is seeking a Principal Systems Engineer to own the compute architecture for RELIC Compute Architecture in Mountain View, CA. You will decide on accelerators, host CPUs, NICs and DPUs, and define scale-up and scale-out fabrics while mapping inference workloads to the platform.

Reporting to the CTO, you will lead device selection, topology decisions and performance models, collaborating with NVIDIA, AMD, and network vendors. This is a hybrid role, three days in office.

Qualifications

• 10+ years in systems architecture for AI, HPC or hyperscale compute.
• Experience with scale-up vs. scale-out and network fabrics.
• Fluency in GPU architecture including SM, tensor cores, HPC memory.
• CPU/host architecture knowledge (Arm, x86, PCIe Gen5/6, CXL).
• Knowledge of modern inference software and disaggregated serving.
• Ability to build quantitative performance and TCO models.
• Active involvement in AI/HPC communities and open-source projects.

Responsibilities

• Define the next-gen RELIC compute platform and select accelerators, CPUs, NICs and DPUs.
• Architect the scale-up domain and optimize NVLink/NVSwitch and rack-scale topology decisions.
• Architect the scale-out and front-end fabrics including RoCEv2, optics, and KV-cache networks.
• Co-design inference stack with hardware, mapping workloads onto platform components.
• Build models for throughput, latency, perf/W and tokens/MW and validate against real data.
• Lead vendor relationships and write architecture specs for procurement and sites.
• Stay hands-on with new platforms to diagnose fabric and node-level issues.

Skills

Systems architecture

Scale-up vs scale-out

GPU architecture fluency

CPU/host architecture

Modern inference software

Quantitative modeling

AI/HPC community involvement

Builder's mindset

Tools

NVLink/NVSwitch

InfiniBand

RoCEv2

SGLang

vLLM

TensorRT-LLM

Dynamo

Job description

Principal Systems Engineer, RELIC Compute Architecture

The role

You will own the compute architecture of next-generation RELIC: what goes in the node, how nodes connect, and how the serving stack maps onto both. Reporting to the CTO, you set the technical direction for every GPU, CPU, NIC, switch and fabric decision we make over the next two hardware generations.

This is a systems role, not a component role. You will reason from model and workload characteristics down to the scale-up domain, the scale-out fabric, memory hierarchy and power envelope, then back up to tokens per second per megawatt and cost per million tokens.

This role is based in our Mountain View, CA. We work hybrid and you’d be in the office three days a week.

What you’ll do

• Define the next-gen RELIC compute platform. Evaluate and select accelerators, host CPUs, NICs and DPUs across NVIDIA (Blackwell Ultra, Rubin), AMD (MI3xx/MI4xx) and emerging inference silicon. Make the call on HGX-class nodes versus rack-scale NVL systems for each site.
• Architect the scale-up domain. Size NVLink/NVSwitch domains and partitioning (e.g. NVL72-class racks), and track open alternatives such as UALink and Ethernet-based scale-up. Decide what domain size each workload actually needs.
• Architect the scale-out and front-end fabrics. Own topology (rail-optimized, fat-tree, multi-plane), RoCEv2 congestion control, Ultra Ethernet readiness, optics and transceiver strategy, and storage and KV-cache networks.
• Co-design the inference stack with the hardware. Map disaggregated prefill/decode, KV-cache transfer and offload, MoE expert parallelism, tensor/pipeline parallelism and speculative decoding onto the platform. Work hands-on with SGLang, vLLM, TensorRT-LLM and NVIDIA Dynamo.
• Build the models that drive decisions. Own performance, roofline and TCO models covering throughput, latency SLOs, perf/W, $/token and tokens/s/MW, and keep them honest against measured data from our clusters.
• Own the roadmap and vendor technical relationships. Lead deep-dives with NVIDIA, AMD, OEMs and network vendors; influence early-access programs; write the architecture specs that procurement and site teams build to.
• Stay close to the metal. Lead bring-up and validation of new platforms and drive root cause on fabric, NIC and node-level issues when they block production.

What you bring

• 10+ years in systems architecture for AI, HPC or hyperscale compute, including at least one platform you took from paper to production at cluster scale.
• Scale-up vs. scale-out, deeply. You can explain when a workload needs a large NVLink domain versus a well-tuned RDMA fabric, and quantify the cost of getting it wrong. Hands-on with NVLink/NVSwitch, InfiniBand and RoCEv2 (PFC, ECN, DCQCN), and familiar with UALink and Ultra Ethernet.
• GPU architecture fluency. SM and tensor-core design, HBM capacity and bandwidth, low-precision formats (FP8, FP4/MXFP4), and how each shows up in prefill versus decode.
• CPU and host architecture. Arm and x86 server cores (e.g. Grace, Neoverse, EPYC, Xeon), NUMA, PCIe Gen5/Gen6, CXL, and the host's role in data movement and KV-cache tiering.
• Modern inference software. Working knowledge of disaggregated serving, continuous batching, paged attention, KV-cache reuse and transfer, and MoE parallelism, with hands-on time in at least one of SGLang, vLLM, TensorRT-LLM or Dynamo.
• Quantitative modeling. You build performance and TCO models from first principles and defend them with benchmarks.
• Embedded in the AI/HPC community. You follow and contribute to the ecosystem: papers, open-source projects, OCP or MLPerf work, conference talks, or deep vendor relationships.
• Builder's temperament. Comfortable owning ambiguous, cross-disciplinary problems at an early-stage company and getting hands dirty in a cluster when needed.

Nice to have

• Silicon or microarchitecture background (CPU, GPU, NPU or network ASIC design or performance architecture).
• Experience with rack-scale systems: liquid cooling, busbar or DC power distribution, 800G/1.6T optics.
• Familiarity with power electronics, DC-coupled architectures, or behind-the-meter power.
• Collective-communication work (NCCL, RCCL, NVSHMEM, NIXL) or HPC experience with MPI-scale jobs.
• Contributions to SGLang, vLLM, Dynamo, LMCache or similar serving projects.
• Experience evaluating non-GPU inference accelerators and building the business case for or against them.
• Published papers or patents in computer architecture, networking or ML systems.