Relocation assistance may be available.
Clearance required for start: Yes. Clearance type: Secret.
Travel: Yes, up to 10% of the time.
Location: San Diego, CA (Northrop Grumman San Diego campus).
We are looking for you to join our team as a Principal Digital Verification Engineer or Senior Principal Digital Verification Engineer.
Responsibilities
- Define and maintain digital logic design verification frameworks and architectures for software‑defined radio systems.
- Develop a verification plan based on digital logic design requirements and design specifications.
- Simulate and verify FPGA logic designs, requirements, and perform system validation.
- Analyze and debug simulation failures, determine root causes of bugs, and work with designers to resolve issues.
- Perform regression testing and generate verification metrics and reporting.
- Operate in a team environment with 5‑7 engineers.
Basic Qualifications – Principal
- Bachelor’s degree in Electrical Engineering or other STEM discipline.
- 5+ years of digital verification engineering experience using industry‑standard simulation tools (3+ years with an MS degree; 1+ years with PhD).
- Experience in VHDL design and verification methodologies for DoD communications systems.
- FPGA deployable product process experience (requirements definition, conceptual design, detailed design, verification, and production release).
- Experience developing verification plans, functional tests, test benches, and bus functional models.
- Experience with forecasting and estimating schedules for assigned tasks.
- Demonstrated strong analytical skills and the ability to prioritize assignments according to program goals.
- Experience using Siemens Questa Simulator.
- Must be a U.S. Citizen with the ability to obtain and maintain a Security Clearance.
Basic Qualifications – Senior Principal
- Bachelor’s degree in Electrical Engineering or other STEM discipline.
- 8+ years of digital verification engineering experience using industry‑standard simulation tools (6+ years with an MS degree; 4+ years with PhD).
- Experience in VHDL design and verification methodologies for DoD communications systems.
- FPGA deployable product process experience (requirements definition, conceptual design, detailed design, verification, and production release).
- Experience developing verification plans, functional tests, test benches, and bus functional models.
- Experience with forecasting and estimating schedules for assigned tasks.
- Demonstrated strong analytical skills and the ability to prioritize assignments according to program goals.
- Experience using Siemens Questa Simulator.
- Must be a U.S. Citizen with the ability to obtain and maintain a Security Clearance.
Preferred Qualifications
- Active Security Clearance.
- Experience with functional verification methodology using OSVVM for the full life cycle of products.
- Experience with scripting languages for Verification automation in a Linux environment (Perl, TCL, Bash, and Makefile).
- Experience using Siemens formal applications such as Lint, Inspect, and CDC.
- Ability to hold special access program clearances.
Salary and Benefits
Primary Level Salary Range: $125,300.00 – $187,900.00. Secondary Level Salary Range: $156,400.00 – $234,600.00.
Employees may be eligible for overtime, shift differential, discretionary bonus, and long‑term incentives for VP/Director positions.
Benefits include health insurance coverage, life and disability insurance, savings plan, company‑paid holidays, and paid time off (vacation and/or personal business).
Equal Opportunity Employer
Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class.