Principal SoC Full-Chip Physical Design Implementation and Verification Engineer

Acara Solutions, An Aleron Company; San Diego (CA); On-site; USD 220,000 - 240,000; Full time

Job summary

A leading company in low power wireless technology is seeking a Principal SoC Full-Chip Physical Design Implementation and Verification Engineer in San Diego. The role involves overseeing the complete SoC design process, ensuring high performance and power efficiency. Candidates should have extensive experience in SoC physical design and verification, with a strong background in RTL-to-GDS flow and full-chip implementation.

Qualifications

• Minimum 10 years of SoC physical design and verification experience.

Responsibilities

• Lead the full-chip implementation and verification of complex SoC designs.
• Oversee the process from RTL development to post-silicon validation.

Skills

Full chip floor planning

Timing ECO implementation

Physical verification

RTL-to-GDS flow

Power efficiency

Education

BSEE or MSEE

PhD

Job description

Principal SoC Full-Chip Physical Design Implementation and Verification Engineer

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Direct message the job poster from Acara Solutions, An Aleron Company

Talent Acquisition Management (Sr. Recruiter) at Acara Solutions

Acara Solutions has been providing staffing services to advanced manufacturing and technology firms since the 1950s. Our client in San Diego (or San Jose), specializing in low power wireless technology, is looking for a Principal SoC Full-Chip Implementation and Verification Engineer to join as a direct salaried employee. The base salary target is $220K, with flexibility up to $240K.

Key qualifications for this principal physical design engineer include:

• Full chip floor planning, bump design, Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
• The entire SoC implementation and verification flow from RTL-to-GDS, including full chip floor plan, place and route, CTS, and layout verification sign-off for lower power SoCs.

The term RTL-to-GDS refers to the complete implementation flow transforming a digital design from RTL (Register Transfer Level) into a GDS (Graphic Data System) file, which is sent to the semiconductor foundry for fabrication. This encompasses the full SoC physical design flow, central to many principal-level SoC engineering roles.

We seek an experienced and innovative engineer to lead the full-chip implementation and verification of complex System-on-Chip (SoC) designs, overseeing the process from RTL development to post-silicon validation, ensuring high performance, reliability, and power efficiency.

Required Skills / Qualifications:

- BSEE or MSEE; PhD is a plus

- Minimum 10 years of SoC physical design and verification experience, including the key responsibilities outlined above

Preferred:

- Wireless low-power experience

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Industries: Computers and Electronics Manufacturing