Principal Product Engineer, Synthesis

Cadence Design Systems, Inc.; San Jose (CA); On-site; USD 136,500 - 253,500; Full time

Benefits offered by this job

Paid vacation

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Job summary

Cadence Design Systems, Inc. in San Jose, California, is seeking a highly motivated engineer to enhance their synthesis and place & route products. This role includes working closely with the R&D team and providing support to customers using Genus solutions.

The ideal candidate should have an MS in Electrical Engineering or ECE, with industrial experience and strong skills in logic design and timing closure. The position offers significant growth opportunities and includes a comprehensive benefits package.

Qualifications

• Requires MS in Electrical Engineering or ECE with focus on VLSI and two or more years of relevant industrial experience.
• Experience in design and EDA emphasizing Cadence tools for Synthesis, Physical Design at 20nm or below.
• Understanding of digital implementation challenges and exposure to 28nm & below foundry process nodes.

Responsibilities

• Perform Product Engineering work for Genus Synthesis Solution.
• Solve challenges in physical aware synthesis and bridge logic synthesis with place and route.
• Support field engineers and interface between R&D and customers.

Skills

Logic Design and Synthesis

Timing Closure

Automation skills using Perl, Tcl, and shell scripting

Strong analysis skills

Education

MS in Electrical Engineering or ECE with focus on VLSI

Tools

Genus

Innovus

Cadence tools of Synthesis

Job description

Job Summary

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Seeking a highly motivated engineer to drive improvement to Cadence’s synthesis and place & route products from a design perspective. The position provides an excellent opportunity to work closely with the R&D team to define the roadmap of the products.

Responsibilities

• Perform Product Engineering work for Genus Synthesis Solution (Genus), a logic synthesis software used for synthesizing a design described in a high-level language into logic gates, to achieve best-in-class Power, Performance & Area (PPA) for latest digital ASICs
• Understand the internal flow within the Genus for newly developed features and verify the correctness and perform experiments to determine an optimal solution
• Solve new and challenging problems in physical aware synthesis space with the goal to bridge the gap between logic synthesis and place and route
• Support the field engineers in Cadence Design Systems, Inc. and its customers in using Genus. In addition, interface between R&D and customer as the first line of support for the R&D and the customers
• Provide support to verify the interoperability of Genus with other digital logic software tools within Cadence Design Systems, Inc. to provide seamless flows

Preferred Qualifications

• Understand the future requirements of the software by interfacing with the internal and external customers of Genus and document the Product Requirement Specifications (PRS) for newly developed features using the standard documentation software
• Requires a MS in Electrical Engineering or ECE with focus on VLSI with two or more years of relevant industrial experience
• Experience in design and EDA with an emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes
• Prior Designer, Product Engineering or Application Engineering experience in digital implementation, especially synthesis
• Understand industry challenges in digital implementation & sign off domain with exposure to 28nm & below foundry process nodes
• Industry experience with EDA tools in the IC digital implementation flow, preferably on Genus and Innovus
• Experience in Logic Design and Synthesis, Formal Verification, Low Power design, Physical Design and Timing Closure for block level and top level designs
• Automation skills using Perl, Tcl and shell scripting essential
• Knowledge of HDL – Verilog or System Verilog is preferred
• Must have logic design and timing closure skills
• Strong analysis skills required to debug complex timing closure, logical and physical design problems. Ability to perform root-cause analysis to suggest solutions to customers and provide feedback to R&D
• Proven track record and experience working in a fast paced environment

The annual salary range for California is $136,500 to $253,500. Benefits: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We are an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.