Principal Process Integration Engineer

NOKIA; San Jose (CA); On-site; USD 165,000 - 225,000; Full time

Job summary

Nokia in San Jose, CA seeks a Principal Process Integration Engineer to ensure quality, reliability and yield of InP-based PIC products. The role focuses on ramping high-volume production, troubleshooting wafer fabrication, and optimizing processes across the fab.

The candidate will lead cross-functional efforts, define process controls, and support next-generation PIC platforms, collaborating with Engineering and Operations to improve throughput and reduce cycle time.

Qualifications

• MS or Ph.D. in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field.
• 10+ years of experience in semiconductor wafer fabrication.
• Hands-on experience with III-V processes (epitaxy, etching, photolithography, metal deposition).
• Strong data analysis and problem-solving with JMP or Python.
• Excellent communication with diverse stakeholders.

Responsibilities

• Own wafer quality and yield using fab process knowledge.
• Analyze process deviations to identify root causes and implement corrective actions.
• Establish inline process specifications and capability (CPK).
• Drive yield improvement from concept through production release.
• Define design rules and test structures for process control.
• Support technology development, transfer, and ramp for next-gen PIC platforms.
• Partner with Process Engineering to improve stability and capability.
• Collaborate with Operations to improve throughput and reduce cycle time.

Skills

Analytical skills

Problem solving

Data analysis

Cross-functional collaboration

Communication

Education

MS or PhD in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or related field

Tools

Python

JMP

DOE

SPC

Job description

The Principal Process Integration Engineer is responsible for ensuring the quality, reliability, and yield of InP-based Photonic Integrated Circuit (PIC) products. This role plays a key part in ramping high-volume production and works cross-functionally to troubleshoot and optimize wafer fabrication processes, resolve yield issues, and support next-generation PIC platform development.

Responsibilities

• Own wafer quality and yield using deep knowledge of fab processes, device physics, and test/reliability data
• Analyze process deviations and test failures to identify root causes and implement corrective actions
• Establish, maintain, and monitor inline fab process specifications and capability (CPK)
• Drive yield improvement initiatives from concept through qualification and production release
• Define design rules and develop test structures for effective process control
• Support technology development, transfer, and manufacturing ramp for next-generation PIC platforms
• Partner with Process Engineering to improve process stability and capability
• Collaborate with Operations to improve throughput and reduce cycle time

Requirements

• MS or Ph.D. in Electrical Engineering, Materials Science, Physics, Chemical Engineering, or a related field
• 10+ years of experience in semiconductor wafer fabrication
• Hands-on experience with III-V processes, including epitaxy, wet and dry etching, photolithography, and metal deposition
• Strong understanding of semiconductor processes and device physics
• Proven analytical and problem-solving skills with proficiency in data analysis tools (e.g., JMP, Python)
• Experience with SPC, DOE, and yield optimization methodologies
• Excellent communication skills with the ability to present technical work to diverse stakeholders