Principal Micro-architect, Coherent Interconnect

Samsung Electronics America; San Jose, Northern (CA, KY); Hybrid; USD 222,000 - 365,000; Full time

Job summary

Samsung Electronics America seeks a Principal Micro-architect to lead the microarchitecture of coherent interconnect IP and LLC blocks for next‑generation designs. You will guide architecture definition, RTL implementation, and collaborate with system architects to optimize performance and power.

You will work with verification, physical design, and CAD teams while mentoring junior engineers. This on‑site role supports Samsung’s SARC/ACL teams with a strong emphasis on scalable, high‑quality IP

Qualifications

• 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering, or 13+ with Master’s, or 11+ with PhD.
• Strong RTL design experience for coherent interconnect and LLC blocks in high‑performance digital designs.
• Expertise spanning architecture definition through RTL implementation.
• Deep knowledge of on‑chip networks (mesh/ring/crossbar) and AMBA protocols.
• Proficient in Verilog/SystemVerilog; solid ASIC flow understanding (STA/DFT/ECO).

Responsibilities

• Lead microarchitecture development of custom coherent interconnect IP and LLC blocks.
• Drive architecture definition from exploration through detailed specifications.
• Collaborate with system architects to shape next‑gen CPU/GPU interconnects.
• Partner with verification teams to ensure functional correctness and validation.
• Develop high‑quality RTL implementations meeting performance, power, and area goals.
• Work with physical design and CAD teams to resolve timing and integration challenges.
• Provide technical leadership and mentor junior engineers.

Skills

RTL design

Coherent interconnect

Verilog/SystemVerilog

Memory subsystem

Mentoring

Education

Bachelor's in Computer Science/Engineering

Master's in CS/CE

PhD in related field

Tools

AMBA5 CHI

AMBA4 ACE

AXI

Job description

## Principal Micro-architect, Coherent InterconnectApply: On-site: 3655 N 1st St, San Jose, CA, USA: 3900 N Capital of Texas Hwy, Austin, TX, USA: Full time: Posted Today: End Date: March 31, 2027 (30+ days left to apply): R121333**Position Summary**Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices consumed by millions of people around the world. Come build with us!**Role and Responsibilities**As a Principal Micro-architect, you will lead the microarchitecture development of custom coherent interconnect IP and/or last-level cache (LLC) blocks for next-generation designs. In this role, you will drive key aspects of coherent interconnect RTL design, including performance and power optimization, logic debug, and timing closure. Success in this role requires a strong foundation in computer architecture, microarchitecture, and RTL design.* Own the development and delivery of custom coherent interconnect IP and/or LLC blocks, ensuring high-quality execution and timely project completion.* Collaborate closely with system architects to define and develop next-generation coherent interconnect and LLC architectures.* Drive microarchitecture definition and specification, from early architectural exploration and microarchitectural research through detailed specification development and refinement.* Partner with verification teams to ensure functional correctness and robust validation of the design.* Develop high-quality RTL implementations that meet performance, power, and area (PPA) goals.* Work with performance and power teams to optimize architecture and RTL implementations for efficiency and scalability.* Collaborate with physical design and CAD teams to resolve implementation, timing, and integration challenges.* Provide technical leadership and mentorship to junior engineers across the team.**Skills and Qualifications*** 15+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 13+ years of experience with a Master’s degree, or 11+ years of experience with a PhD* Strong background driving RTL design of coherent interconnect and LLC sub-blocks for high-performance digital designs* Demonstrated experience spanning architecture definition through RTL implementation* Familiarity with on-chip network topologies such as mesh, ring, and crossbar interconnects, along with working knowledge of Arm AMBA5 CHI, AMBA4 ACE, AXI, and related coherent interconnect protocols.* Deep expertise in Verilog/SystemVerilog and solid understanding of the complete ASIC design flow including STA, DFT, ECO flows, etc.* Strong understanding of memory subsystem architecture, coherent cache design, system caches, coherency mechanisms, and directory-based snoop filter protocols.* Proven experience leading technical initiatives, mentoring engineers, and collaborating effectively across dynamic, geographically distributed teams with strong communication and interpersonal skills.* Experience with a scripting language like Perl or Python is a plus**Our Team** Our System IP team develops proprietary coherent interconnect and memory controller deployed in many high-volume products. Our team plays a key role in influencing the product roadmap for a market-leading system IP solutions. We focus on delivering system modeling capability based on optimization and use-case-driven analysis (gaming, computational photography) that enables a world-class memory subsystem.With architecture scalability at the frontier of our design focus, our performance- and power-optimized IP solution gets integrated into complex semiconductor products, aiming to reach multiple market segments.Being part of a new team of talented individuals with vastly diverse backgrounds and skill sets at a well-established global company means you have limitless room to explore, innovate, and expand role responsibilities to build technical expertise. With a big charter ahead, we get to do challenging work and solve unique problems in a highly collaborative and supportive environment. You will always be learning while helping us shape the team’s culture.**Total Rewards** At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $221,700 and $364,800. Your actual base pay will depend on variables that may include your education skills, qualifications, experience, and work location. This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).Samsung employees have access to benefits including: medical, dental, vision, life insurance, 401(k), free onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, wellness incentives, and many more. In addition, regular full-time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.Additionally, this role might be eligible to participate in long term incentive plan and relocation.**Trade Secrets** By submitting an application, you agree not to disclose to Samsung or induce or encourage Samsung to use any confidential or proprietary information (including trade secrets) belonging to a current or former employer or other entity.**U.S. Export Control** This role may require access to information subject to U.S. export control laws. Applicants must be authorized to access such information or eligible for government authorization.