Principal FPGA Software Engineer - DSP/Data-Processing

Northrop Grumman; El Segundo (CA); On-site; USD 92,000 - 171,000; Full time

Job summary

Northrop Grumman Aeronautics Systems in El Segundo, CA seeks a Software Engineer/Principal Software Engineer to design, implement, verify, and optimize high-performance FPGA-based hardware for a range of military applications. Onsite work with a diverse team across cutting-edge technologies is required.

The role emphasizes HDL design, simulations, place‑and‑route, Lab/SIL integration, and FPGA‑SoC code to enable end-to-end functionality.

Qualifications

• Bachelor’s Degree in a STEM discipline with 2 years of related engineering experience; OR Master’s in STEM with 0 years of experience.
• Principal Software Engineer requires 5 years with Bachelor’s, or 3 years with Master, or PhD with 0+ years of experience.
• Ability to obtain and maintain final adjudicated Secret clearance.
• Proven FPGA development experience for DSP/data-processing applications.
• Experience in running simulations and place-and-route; lab/SIL integration.

Responsibilities

• Develop FPGA designs for DSP and data-processing applications.
• Perform FPGA simulations and verify functional correctness.
• Execute place-and-route flows and optimize timing.
• Integrate and test systems in lab environments and SILs.
• Incorporate FPGA-SoC code to enable end-to-end functionality.

Skills

FPGA development

DSP/data-processing

Lab/SIL integration

FPGA-SoC code

HDL design

Verification methodologies

Education

Bachelor’s Degree in STEM

Master’s Degree in STEM

PhD in STEM

Tools

Simulation tools

Place-and-route tools

Lab equipment

Job description

Northrop Grumman Aeronautics Systems in El Segundo, CA seeks a Software Engineer/Principal Software Engineer to design, implement, verify, and optimize high-performance FPGA-based hardware for a range of military applications. Onsite work with a diverse team across cutting-edge technologies is required.

The role emphasizes HDL design, simulations, place‑and‑route, Lab/SIL integration, and FPGA‑SoC code to enable end-to-end functionality.