Principal FPGA Engineer

Prattwhitney; McKinney (TX); On-site; USD 107,500 - 204,500; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) match

Flexible work schedules

Job summary

Prattwhitney is looking for a Principal Electrical Engineer – FPGA Lead based in McKinney, Texas. The role involves providing technical leadership in designing high-quality FPGA products and managing teams effectively.

Ideal candidates will have extensive FPGA/ASIC design experience with VHDL or Verilog, complemented by strong project management skills. A competitive salary range from 107,500 to 204,500 USD is offered along with various benefits.

Qualifications

• Minimum 8 years of experience in relevant FPGA/ASIC design or verification.
• Experience with timing closure and project management tools.
• Demonstrated mentorship and leadership skills.

Responsibilities

• Lead full lifecycle support of production quality FPGA designs.
• Generate detailed FPGA designs and verify utilizing testing techniques.
• Coach and manage junior engineers, lead technical reviews.

Skills

FPGA design

VHDL

Team leadership

System Verilog

Project management

Education

STEM degree

Advanced degrees in Electrical Engineering

Tools

AMD Vivado

Altera Quartus Prime Pro

Libero

Job description

Principal Electrical Engineer – FPGA Lead

Date Posted: 2026-03-05
Location: McKinney, TX, USA
Position Type: Onsite
Security Clearance: Must obtain and maintain a U.S. government issued DoD Secret clearance. U.S. citizenship is required.

Overview

At Raytheon Technologies, the Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for missiles, radars, and electronic warfare systems. The team leverages digital, analog, and power design skills to support the product lifecycle from architecture through production and sustainment. This role serves as the Field Programmable Gate Array Lead, providing technical leadership across the organization.

Responsibilities

• Provide full lifecycle support of production quality FPGA designs for all major vendors and device families, including AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro, or Libero.
• Generate FPGA designs for gigabit and multigigabit transceiver (MGT) serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing, and processor interfaces.
• Translate system level requirements into FPGA requirements.
• Architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS).
• Lead small teams of FPGA engineers and code in VHDL for reliability and maintainability.
• Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage.
• Define schedules for FPGA tasking and drive execution to the planned budget and schedule.
• Identify and manage project risks and opportunities.
• Create complete documentation including requirements, verification plans, and user’s guides.
• Lead medium sized teams to success.
• Coach, review, and delegate work to junior engineers.
• Serve as a subject‑matter expert within the discipline.
• Lead internal and external technical reviews.
• Support customer interactions and relations.
• Contribute to product and technology roadmaps.
• Make improvements to processes, systems or products to enhance overall performance.
• Engage in personal technical growth and facilitate technical growth in peers and junior engineers.

Qualifications

• Typically requires a STEM degree and a minimum of 8 years of prior relevant experience.
• Experience with FPGA/ASIC design (VHDL and/or Verilog) or verification (System Verilog) and with AMD (Xilinx), Altera, and/or Microchip (Microsemi) devices and tools such as AMD Vivado, Altera Quartus Prime Pro, or Libero.
• Hands‑on experience with integration and debugging of FPGA/ASIC in a lab environment.
• Experience with timing closure, clock domain crossing, and reset domain crossing analysis, and constraint development.
• Experience with source code management, design reviews, and code release in a team development environment.
• Advanced degrees in Electrical Engineering or a related STEM field are valued.
• FPGA/ASIC design experience in radar processing, image processing for visual and infrared sensors, embedded systems design using ARM, Microblaze, or NIOS processors, gigabit serial interfaces, and multigigabit transceivers.
• Constrained random verification in UVM using System Verilog and verification on emulation platforms such as Veloce.
• Experience with High Level Synthesis (HLS), vector processors and/or GPUs, and using AI to improve FPGA workflows (verification automation, log triage, regression analytics).
• Experience with AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators).
• Demonstrated ability to lead successful teams and manage technical, cost, and schedule risks.
• Experience with project management tools such as Earned Value and/or Agile Execution.
• Experience communicating and documenting technical topics and presenting to customers and management.
• Experience leading a program transition from development to production.
• Proposal development experience and intellectual property generation (patents & publications).
• Demonstrated mentorship of junior engineers.

Benefits

This position offers relocation based on candidate eligibility. The salary range is 107,500 USD – 204,500 USD. Benefits may include medical, dental, vision, life insurance, short‑term disability, long‑term disability, 401(k) match, flexible spending accounts, flexible work schedules, employee assistance program, parental leave, paid time off, holidays, and incentive compensation programs. Specific benefits depend on the business unit and collective‑bargaining agreement status.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other applicable state or federal protected class.

Security Clearance

The DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the Department of Defense, handles and adjudicates the security clearance process. More information about Security Clearances can be found on the US Department of State government website: https://www.state.gov/m/ds/clearances/c10978.htm.