Principal FPGA Digital Engineer - 3

Northrop Grumman; United States; On-site; USD 108,000 - 162,000; Full time

Job summary

Northrop Grumman Space Systems seeks a Principal FPGA Digital Engineer in Chandler, AZ to design, verify, and integrate FPGA/SoC hardware modules. You will work with cross-disciplinary teams to resolve design and integration challenges and develop advanced test benches to ensure functional and timing correctness.

Ideal candidates have FPGA/VHDL or Verilog expertise, hands-on with Vivado, OSVVM/UVM knowledge, and the ability to obtain a DoD Secret clearance.

Qualifications

• Bachelor's degree in Electrical or Computer Engineering or related field with 5+ years of experience; or advanced degrees with fewer years.
• Ability to obtain DoD Secret clearance at time of application.
• Strong FPGA/SoC design background with VHDL/Verilog.
• Experience with AMD Xilinx FPGAs/SoCs and timing analysis using Vivado.
• Experience with MOSA/DP architecture, interfaces and verification.
• Knowledge of OSVVM or UVM is preferred.

Responsibilities

• Collaborate with senior FPGA engineers and cross-disciplinary teams to address design challenges.
• Develop and execute test benches to verify functional and timing requirements.
• Create and integrate HDL modules and IO/image processing blocks; ensure design compliance.
• Manage multiple FPGA bitstream configurations and documentation.
• Stay updated on FPGA tools/techniques and industry standards.

Skills

FPGA design

VHDL/Verilog

Vivado IDE

OSVVM

UVM

SoC integration

Education

Bachelor's in Electrical/Computer Engineering

Tools

Questa/ModelSim

Oscilloscopes

Logic analyzers

Job description

RELOCATION ASSISTANCE: Relocation assistance may be available

CLEARANCE REQUIRED FOR START: Yes

CLEARANCE TYPE: Secret

TRAVEL: Yes, 10% of the Time Description

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Northrop Grumman Space Systems is looking for a Principal FPGA Digital Engineer to support the Electro-Optics (EO) Group within the Launch Vehicles business unit in Chandler, Arizona.

As a principal FPGA design engineer, you will work closely with senior FPGA engineers and cross-disciplinary teams (hardware, algorithms, and software) to address design challenges and ensure seamless hardware integration. This role will focus on developing and executing test benches to independently validate FPGA designs for functional correctness and timing requirements, while adhering to internal design standards. The ideal candidate excels in fast-paced, collaborative environments and is comfortable managing multiple diverse assignments.

Responsibilities :

• Collaborate with senior FPGA engineers and multidisciplinary teams (hardware, algorithms, software) to resolve design and integration challenges
• Develop and execute advanced test benches to verify that FPGA designs meet functional and timing requirements
• Generate, verify & integrate IO and image processing HDL modules. including functions definitions, HDL coding, module level sim and integration with overall device architecture
• Ensure compliance with internal design standards throughout the development lifecycle
• Oversee configuration management of multiple FPGA bitstream build configurations to support varied use cases or platform requirements
• Prepare, present, and maintain comprehensive design documentation, including schematics, simulation results, and verification reports
• Continuously expand technical knowledge by staying abreast of evolving FPGA technologies, tools, and industry methodologies

Basic Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university and 5 years of relevant experience; or a Master's degree and 3 years of experience; or a PhD and 1 year of experience.
• Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application.
• Solid background in FPGA/SoC design, including complex firmware development using VHDL (preferred) or Verilog.
• Significant experience with AMD Xilinx FPGAs and SoCs.
• Knowledgeable in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets using Vivado IDE;
• Proficient in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC)
• Competency with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
• Creating and executing verification plans using simulation, analysis, and hardware bench testing.
• Understanding of Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferred

Preferred Qualifications:

• MS or PhD in Electrical Engineering, Computer Engineering, or related discipline.
• Active U.S. Government DoD Secret security clearance at the time of application.
• Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications.
• Previous experience or knowledge of DoD missile defense programs and associated standards.
• Direct experience with AMD Xilinx Versal Gen 2 or Gen 1
• Advanced experience with both Vivado IDE and Vitis Unified IDE.
• Experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) and fabric-based controllers (such as AXI or custom interconnects) in FPGA designs, including expertise in IP configuration, timing closure, signal integrity, and high-throughput data movement.
• Understanding of embedded C/C++ programming for integration with processors/SoCs
• Knowledge of high-speed PCB design and signal integrity
• Strong experience with OSVVM or UVM.

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Primary Level Salary Range: $108,200.00 - $162,400.00

The above salary range represents a general guideline; however, Northrop Grum