Staff FPGA Digital Engineer - 5

Northrop Grumman Corp.; Chandler (AZ); On-site; USD 108,000 - 162,000; Full time

Benefits offered by this job

Relocation assistance

Secret clearance

Travel opportunities

Job summary

Northrop Grumman Space Systems in Chandler, AZ is seeking a Staff FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will apply advanced FPGA engineering principles, lead design challenges, and develop high-level test benches for timing-critical FPGA designs.

The role requires mastery of VHDL/Verilog, extensive Xilinx FPGA/SoC experience, and verification with OSVVM/UVM and Questa/ModelSim. Travel up to 10% may be required and DoD Secret clearance is required.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university.
• Advanced background in FPGA/SoC design with mastery in complex firmware development using VHDL (preferred) or Verilog.
• Extensive experience with AMD Xilinx FPGAs and SoCs, managing design constraints (timing, power, I/O) and performing static timing analysis.

Responsibilities

• Lead resolution of design and integration challenges across hardware, algorithms, and software teams.
• Develop and execute high-level test benches to verify FPGA designs for timing and functional correctness.
• Generate, verify, and integrate HDL modules and interfaces (Ethernet, PCIe, AXI4, UART, SDLC).
• Prepare, present, and maintain design documentation and verification reports.
• Stay abreast of evolving FPGA technologies and tools.

Skills

FPGA design

VHDL/Verilog

Xilinx FPGAs/SoCs

OSVVM/UVM verification

Questa/ModelSim

Timing analysis

DDR memory interfaces

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline

MS or PhD in Electrical Engineering, Computer Engineering, or related discipline

Tools

Vivado IDE

Vitis Unified IDE

OSVVM

OSVVM/UVM tooling

Questa/ModelSim

Logic analyzers

Oscilloscopes

Job description

RELOCATION ASSISTANCE: Relocation assistance may be availableCLEARANCE REQUIRED FOR START: YesCLEARANCE TYPE: SecretTRAVEL: Yes, 10% of the TimeDescriptionAt Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.Northrop Grumman Space Systems is looking for a Staff FPGA Digital Engineer to support the Electro-Optics (EO) Group within the Launch Vehicles business unit in Chandler, Arizona.As a Staff FPGA design engineer, you will apply advanced understanding and wide application of FPGA engineering principles, including mastery of methods and tools available for solving complex technical challenges. You will work closely with senior staff, junior staff, and cross-disciplinary teams (hardware, algorithms, and software) to provide technical solutions to a wide range of complex problems. The ideal candidate excels in fast-paced, collaborative environments and is comfortable managing multiple diverse assignments.Responsibilities:Lead resolution of design and integration challenges, drawing on advanced technical knowledge and wide application across disciplines.Develop and execute high-level test benches to verify FPGA designs for functional correctness and timing requirements, managing configuration of multiple FPGA bitstream builds.Generate, verify, and integrate IO and image processing HDL modules, including functions definitions, HDL coding, module-level simulation, and integration with device architecture.Ensure compliance with internal design standards throughout the development lifecycle and mentor less experienced engineers.Prepare, present, and maintain comprehensive design documentation including schematics, simulation results, and verification reports.Stay abreast of evolving FPGA technologies, tools, and industry methodologies, demonstrating mastery in methods and tools available for addressing technical issues.Basic Qualifications:Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline from an accredited university and 12 years of relevant experience; or a Master’s degree and 10 years of experience; or a PhD and 8 years of experience.Ability to obtain a U.S. Government Department of Defense (DoD) Secret security clearance at the time of application.Advanced background in FPGA/SoC design, with mastery in complex firmware development using VHDL (preferred) or Verilog.Extensive experience with AMD Xilinx FPGAs and SoCs, with proficiency in managing design constraints (timing, power, I/O) and performing static timing analysis to achieve critical performance targets.Advanced proficiency in development, verification, and debugging of MOSA interfaces/buses (Ethernet, PCIe, AXI4, UART, and SDLC)Mastery with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).Strong experience creating and executing verification plans using simulation, analysis, and hardware bench testing.Deep knowledge of Open Source VHDL Verification Methodology (OSVVM) or Universal Verification Methodology (UVM). OSVVM preferredPreferred Qualifications:MS or PhD in Electrical Engineering, Computer Engineering, or related discipline.Active U.S. Government DoD Secret security clearance at the time of application.Experience with missile systems, seeker systems, or other high reliability, environmentally challenging electro optical applications.Prior experience with DoD missile defense programs and associated standards.Direct experience with AMD Xilinx Versal Gen 2 or Gen 1Mastery with both Vivado IDE and Vitis Unified IDE.Advanced experience designing, integrating, and verifying DDR memory interfaces (e.g., DDR3/DDR4/DDR5) with fabric-based controllers in FPGA designs.Deep understanding of embedded C/C++ programming for integration with processors/SoCs.Knowledge of high-speed PCB design and signal integrity.Strong experience with OSVVM or UVM.Primary Level Salary Range: $108,200.00 - $162,400.00The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives. In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO. U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.