Principal Engineer, Physical Design (ASIC Place & Route) (San Jose, CA) (7429)

TSMC; San Jose (CA); Hybrid; USD 140,000 - 220,000; Full time

Job summary

TSMC is seeking a Principal Physical Design Engineer in San Jose, CA to drive end-to-end physical design for ASICPlace & Route. You will lead multi-million gate blocks through synthesis, floorplanning, placement, CTS, routing, and signoff, ensuring robust PDN and minimized congestion in a hybrid on-site role.

The ideal candidate has 10+ years in full-chip design, deep EDA tool mastery, and strong scripting skills.

Qualifications

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Microelectronics, or closely related field.
• 10+ years of hands-on full-chip or block-level physical design implementation and signoff with tapeouts.
• Proven mastery of industry-standard EDA tool suites (Synopsys Fusion Compiler/ICC2, PrimeTime, StarRC; Cadence Innovus, Tempus, Voltus; Siemens Calibre).
• Proven track record implementing designs in TSMC N16/N12 or below with deep knowledge of parasitic extraction, multi-patterning, and variability effects.

Responsibilities

• Drive full-flow RTL/Netlist-to-GDSII physical implementation across blocks and chips.
• Architect optimized floorplans and robust PDN to minimize congestion and macro placement overhead.
• Synthesize clock trees with low skew and variation-aware timing margins.
• Lead ECOs across multi-corner, multi-mode scenarios for reliable signoff.
• Debug DRC/LVS/ERC/antenna issues and align with foundry DRMs.
• Develop automation frameworks using Tcl and Python to speed tapeout and cross-project predictability.

Skills

EDA tool mastery

Scripting (Tcl/Perl/Python)

Leadership & collaboration

On-site collaboration

Education

Master’s or Ph.D. in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler/ICC2

PrimeTime

StarRC

Cadence Innovus

Tempus

Voltus

Siemens Calibre

Job description

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Principal Engineer, Physical Design (ASIC Place & Route) (San Jose, CA) (7429)

Overview of Role

As a Principal Physical Design Engineer, you will serve as a foundational pillar in translating complex architectural concepts into high-yield, production-ready silicon. Operating at the cutting edge of semiconductor design, you will spearhead end-to-end netlist-to-GDSII implementation for ultra-large-scale, high-performance computing (HPC) and AI silicon architectures. In this role, you will define the boundaries of achievable PPA (Power, Performance, and Area) across the industry’s most advanced process nodes.

Based out of our San Jose Center of Excellence and working closely with our customer partners, you will collaborate with cross-functional architecture, CAD, and DFT teams to push physical design methodologies forward. You will lead technical execution on critical block- and chip-level domains, tackling non-trivial physical and electrical challenges inherent to deep-submicron physics.

We are seeking a seasoned, intellectually curious individual who thrives on engineering rigor and structural precision. This position follows a high-impact, hybrid collaboration model (4 days on-site) designed to accelerate tight engineering feedback loops and direct technical partnership.

Responsibilities

• Drive full-flow RTL/Netlist-to-GDSII physical implementation, taking high-complexity, multi-million gate blocks through synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and final signoff.
• Architect highly optimized floorplans from scratch, establishing robust power delivery networks (PDN) while strategically minimizing congestion, channel utilization, and macro placement overhead.
• Synthesize customized, low-skew, and variation‑aware clock tree architectures designed to maximize frequency margins under aggressive power budgets.
• Execute advanced timing closure and post‑route optimization workflows, methodically engineering functional and timing engineering change orders (ECOs) across multi‑corner, multi‑mode (MCMM) scenarios.
• Mitigate complex electrical and physical phenomena by leading deep‑dive signal electromigration (EM), dynamic cross‑talk noise, and power rail integrity (IR drop) analyses to guarantee target reliability margins.
• Direct physical verification signoff by debugging and rectifying complex DRC, LVS, ERC, and antenna violations in close alignment with advanced foundry design rule manuals (DRMs).
• Develop and deploy bespoke automation frameworks and design methodology enhancements using Tcl and Python/Perl to streamline tapeout velocity and improve cross‑project PPA predictability.

Minimum Qualifications

• Master’s or Ph.D. degree in Electrical Engineering, Computer Engineering, Microelectronics, or a closely related technical field.
• 10+ years of direct, hands‑on experience in full‑chip or block‑level physical design implementation and signoff with a proven track record of successful tapeouts.
• Demonstrated mastery of industry‑standard EDA tool suites (e.g., Synopsys Fusion Compiler/ICC2, PrimeTime, StarRC; Cadence Innovus, Tempus, Voltus; Siemens Calibre).
• Proven track record implementing designs in TSMC N16/N12 or below, with deep knowledge of advanced FinFET parasitic extraction, multi‑patterning, and variability effects.
• Proficient scripting ability in Tcl, Perl, and/or Python to construct, maintain, and debug complex automation pipelines and signoff scripts.
• Strong communication and cross‑functional leadership skills, with the flexibility to work regularly on‑site and at key customer partner facilities across the South Bay Area.

Preferred Qualifications

• Hands‑on physical design and tapeout experience on advanced FinFET/GAA nodes (TSMC N5, N4, N3, or below).
• Advanced expertise in low‑power methodology implementation, including multi‑voltage domains, dynamic/static power gating (UPF/CPF), and retention strategies.
• In‑depth understanding of advanced timing signoff paradigms, such as POCV (Parametric On‑Chip Variation), advanced OCV, and hyper‑convergent signoff flows.
• Demonstrated leadership in leading cross‑functional task forces through critical tapeout milestones and complex foundry‑interface debug cycles.

Company Description

Join TSMC Technology, Inc. (TTI), an innovation hub of Taiwan Semiconductor Manufacturing Company Limited (TSMC). TSMC has been a pioneer in the semiconductor industry since 1987. With teams located in San Jose, CA, and Austin, TX, TTI is dedicated to advancing semiconductor technology through expertise in physical design, memory design, analog mixed signal, power management, and groundbreaking computational AI machine learning research. Our mission is to drive the future of semiconductor innovation through unparalleled R&D and customer‑focused IP. Be part of a team that shapes the next generation of technological advancements.

As a trusted technology and capacity provider, TSMC is driven by the desire to be:

• The world’s leading dedicated semiconductor foundry
• The technology leader with a strong reputation for manufacturing excellence
• Advancing semiconductor manufacturing innovations to enable the future of technology

TSMC pioneered the pure‑play foundry business model when it was founded in 1987 and has been the world’s leading dedicated semiconductor foundry ever since. The Company supports a thriving ecosystem of global customers and partners with the industry’s leading process technologies and a portfolio of design enablement solutions to unleash innovation for the global semiconductor industry. With global operations spanning Asia, Europe, and North America, TSMC serves as a committed corporate citizen around the world.

In North America, TSMC has a strong sales and service organization that works with customers by helping them achieve silicon success with cutting‑edge technologies and manufacturing excellence. The Company has continued to accelerate its R&D investment and staffing in recent years and is expanding its manufacturing footprint to support customer innovation with 3D IC technologies and optimal manufacturing capacity.

For positions requiring access to technical data subject to export control regulations, including Export Administration Regulations, TSMC Technology Inc. may have to obtain export licensing approval from the U.S. Government for certain individuals. All employment is contingent upon TSMC Technology Inc. obtaining any export license or other approval that may be required by the U.S. Government.

TSMC Core Values

At TSMC, we invite talented individuals who share our vision and values to contribute to our continued success. Our core values are the foundation of our culture, guiding every decision and action. We seek applicants who deeply resonate with these principles and embody them in their work:

Integrity: Tell the truth. We do not brag. We do not make commitments lightly. Once we make a commitment, we devote ourselves completely to meeting that commitment.

Commitment: Employees are dedicated to the company, view the company’s success as their own and work diligently to make their best contributions. As commitment is mutual, the Company strives to serve the best interests of its employees.

Innovation: Innovation is the wellspring of the Company’s growth. It means more than new ideas; it means putting ideas into practice.

Customer Trust: We strive to build deep and enduring relationships with our customers, who trust and rely on us to be part of their success over the long term.

TSMC Technology, Inc. is committed to employing a diverse workforce and provides Equal Employment Opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, status as a protected veteran, genetic information, or any other characteristic protected by applicable law.

TSMC is an equal opportunity employer prizing diversity and inclusion. We are committed to treating all employees and applicants for employment with respect and dignity. If you require reasonable accommodation due to a disability during the application or the recruiting process, please feel free to notify us at [e-mail] . TSMC confirms to all applicants its commitment to meet TSMC’s obligations under applicable employment law. Reasonable accommodations will be determined on a case‑by‑case basis.

Pay Transparency / Benefits statement

At TSMC, your base pay is only part of your overall total compensation package. At the time of this posting, this role typically pays a base salary between $140,000 and $220,000 per year. The range displayed reflects the minimum and maximum target for new hires. Actual pay may be more or less than the posted range. Factors that influence pay include the individual's skills, qualifications, education, experience and the position level and location. TSMC’s total compensation package consists of market competitive pay, allowances, bonuses, and comprehensive benefits. We also offer extensive development opportunities and programs.