Sr. RTL Design Engineer

Rivian; Palo Alto (CA); On-site; USD 146,000 - 183,000; Full time

Benefits offered by this job

401(k) Plan

Employee Stock Purchase Program

Comprehensive benefits package

Job summary

Rivian is seeking an RTL Design Engineer in Palo Alto to craft production‑quality RTL for the Neural Network Engine (NNE) in an advanced SoC environment.

You will translate architectural requirements into clean SystemVerilog, validate with verification, and drive block ownership from definition through integration with design and silicon validation teams.

Qualifications

• Bachelor’s degree or equivalent practical experience in EE/CE or related field.
• Professional experience delivering synthesizable RTL for ASIC/SoC or similar.
• Strong proficiency in Verilog and SystemVerilog.
• Understanding of synchronous digital design, pipelining and FSMs.
• Experience debugging RTL through simulation and waveform analysis.

Responsibilities

• Design, implement, integrate, and debug synthesizable RTL for NNE blocks and interfaces.
• Translate specs into clear, maintainable RTL and supporting design docs.
• Develop pipelined datapaths, control logic, FSMs, queues, memories, and configuration logic.
• Define and review block interfaces, data movement, clocking, reset behavior, and error handling.
• Develop AI agents to streamline RTL development tasks.
• Design with performance, power, area, and safety constraints in mind.
• Collaborate with verification engineers to create test plans, coverage goals, and debug strategies.
• Use simulation, lint, CDC/RDC, formal or equivalence checking, synthesis, and timing analysis.
• Investigate issues across RTL, verification, and implementation flows.
• Participate in design reviews and improve coding standards and reusable RTL patterns.
• Support block integration, regression closure, RTL handoff, and pre-silicon validation.
• Communicate design decisions, risks, and trade-offs across teams.

Skills

Verilog

SystemVerilog

Architectural specs

RTL design

Verifications collaboration

Communication

Education

Bachelor’s degree in Electrical/Computer Engineering or related field

Tools

Synopsys VCS

Verdi

Job description

About Rivian

Rivianis on a mission to keep the world adventurous forever. This goes for the emissions-free Electric Adventure Vehicles we build, and the curious, courageous souls we seek to attract.

As a company, we constantly challenge what’s possible, never simply accepting what has always been done. We reframe old problems, seek new solutions and operate comfortably in areas that are unknown. Our backgrounds are diverse, but our team shares a love of the outdoors and a desire to protect it for future generations.

Role Summary

We are seeking an RTL Design Engineer to join the Neural Network Engine (NNE) design team in Palo Alto. In this hands‑on role, you will design and deliver production-quality RTL for compute, memory, datapath, and control blocks in an advanced SoC environment.

You will work from architectural and microarchitectural requirements, turn them into clean and synthesizable SystemVerilog, and partner closely with design verification, physical design, firmware, compiler, and silicon-validation engineers. The ideal candidate is comfortable owning a block from definition through implementation, debug, quality checks, and integration.

Responsibilities

• Design, implement, integrate, and debug synthesizable RTL for NNE blocks and interfaces.
• Translate architectural and microarchitectural specifications into clear, maintainable RTL and supporting design documentation.
• Develop pipelined datapaths, control logic, finite-state machines, queues, counters, memory interfaces, and configuration/status logic.
• Define and review block‑level interfaces, including data movement, handshakes, clocking, reset behavior, and error handling.
• Develop and utilize AI agents to streamline RTL development tasks
• Design with performance, power, area, functional safety, and physical implementation constraints in mind.
• Collaborate with design verification engineers to create test plans, assertions, coverage goals, and debug strategies.
• Use simulation, lint, CDC/RDC, formal or equivalence checking, synthesis, and timing analysis to evaluate and improve RTL quality.
• Investigate functional, performance, timing, and power issues across RTL, verification, and implementation flows.
• Participate in design reviews and contribute to coding standards, reusable RTL patterns, and development methodology improvements.
• Support block integration, regression closure, RTL handoff, and pre‑silicon validation.
• Communicate design decisions, assumptions, risks, and trade‑offs clearly across partner teams.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent practical experience.
• Professional experience designing and delivering synthesizable RTL for ASIC, SoC, or other complex digital hardware.
• Strong proficiency in Verilog and SystemVerilog.
• Understanding of synchronous digital design, pipelining, finite-state machines, interfaces, memories, and reset/clock behavior.
• Experience debugging RTL through simulation and waveform analysis.
• Ability to read and contribute to architectural, microarchitectural, interface, and verification specifications.
• Strong written and verbal communication skills, especially to write clear design documentation, with a collaborative and ownership‑oriented approach.
• A disciplined approach to writing simple, readable, reusable, and verifiable RTL.
• Curiosity about how architecture, implementation, verification, and physical design interact.
• Comfort working through ambiguous problems, making explicit assumptions, and iterating with partner teams.
• A bias toward early validation, clear documentation, and high‑quality handoffs.
• The ability to balance block‑level ownership with system‑level thinking.

Preferred qualifications

• Experience with compute engines, neural‑network accelerators, floating point computation, memory subsystems, high‑throughput datapaths, or SoC control logic.
• Experience with clock‑domain crossings, reset‑domain crossings, clock gating, power‑aware design, or functional‑safety concepts.
• Familiarity with RTL quality and implementation flows such as lint, CDC/RDC, formal/equivalence checking, synthesis, static timing analysis, and power analysis.
• Experience with Synopsys VCS, Verdi, or comparable simulation and debug tools.
• Experience building Python or other software models to explore architecture, validate behavior, or accelerate RTL development.
• Experience with Git‑based development, code review, continuous integration, and automated regressions.
• Familiarity with physical‑design constraints and PPA trade‑offs.
• Experience working across hardware, firmware, compiler, verification, physical design, and silicon‑validation teams.
• Experience developing hardware for automotive, safety‑critical, or other reliability‑sensitive applications.

Pay Disclosure

The listed base salary range for this role is $146,00 - $183,000 for San Francisco Bay Area based applicants. This is the lowest to highest salary we in good faith believe we would pay for this role at the time of this posting. An employee’s position within the salary range will be based on several factors including, but not limited to, specific competencies, relevant education, qualifications, certifications, experience, skills, geographic location, shift, and organizational needs.

We offer a comprehensive package of benefits for full‑time and part‑time employees, their spouse or domestic partner, and children up to age 26, including but not limited to paid vacation, paid sick leave, and a competitive portfolio of insurance benefits including life, medical, dental, vision, short‑term disability insurance, and long‑term disability insurance to eligible employees. You may also have the opportunity to participate in Rivian's 401(k) Plan and Employee Stock Purchase Program if you meet certain eligibility requirements. Full‑time employee coverage is effective on their first day of employment. Part‑time employee coverage is effective the first of the month following 90 days of employment. More information about benefits is available at rivianbenefits.com.

Equal Opportunity

Rivian is an equal opportunity employer and complies with all applicable federal, state, and local fair employment practices laws. All qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, ancestry, sex, sexual orientation, gender, gender expression, gender identity, genetic information or characteristics, physical or mental disability, marital/domestic partner status, age, military/veteran status, medical condition, or any other characteristic protected by law.

Rivian is committed to ensuring that our hiring process is accessible for persons with disabilities. If you have a disability or limitation, such as those covered by the Americans with Disabilities Act, that requires accommodations to assist you in the search and application process, please email us at [e-mail].

Candidate Data Privacy and Technology

Rivian may collect, use and disclose your personal information or personal data (within the meaning of the applicable data protection laws) when you apply for employment and/or participate in our recruitment processes ("Candidate Personal Data"). This data includes contact, demographic, communications, educational, professional, employment, social media/website, network/device, recruiting system usage/interaction, security and preference information. Rivian may use your Candidate Personal Data for the purposes of (i) tracking interactions with our recruiting system; (ii) carrying out, analyzing and improving our application and recruitment process, including assessing you and your application and conducting employment, background and reference checks; (iii) establishing an employment relationship or entering into an employment contract with you; (iv) complying with our legal, regulatory and corporate governance obligations; (v) recordkeeping; (vi) ensuring network and information security and preventing fraud; and (vii) as otherwise required or permitted by applicable law.

Rivian may share your Candidate Personal Data with (i) internal personnel who have a need to know such information in order to perform their duties, including individuals on our People Team, Finance, Legal, and the team(s) with the position(s) for which you are applying; (ii) Rivian affiliates; and (iii) Rivian's service providers, including providers of background checks, staffing services, and cloud services.

Rivian may transfer or store internationally your Candidate Personal Data, including to or in the United States, Canada, the United Kingdom, and the European Union and in the cloud, and this data may be subject to the laws and accessible to the courts, law enforcement and national security authorities of such jurisdictions.

How We Use AI in Our Hiring Process: To ensure transparency, we want candidates to know that Rivian uses iCIMS Talent Cloud Artificial Intelligence (TCAI) and AI-enabled tools to assist with screening, reviewing, organizing and highlighting profiles and applications that match the key requirements for each role.

AI does not make hiring decisions: Qualified candidate applications are reviewed by a member of our team, and all decisions throughout the process are made by humans. We use AI to support efficiency and consistency, not to replace human judgment. We are committed to a fair, thoughtful, and equitable experience for every candidate.

Participation in AI profile matching is entirely voluntary. If you prefer that your profile not be used in this process, you can opt out at any time. Opting out means your profile will be excluded from automated matching and will not be surfaced for additional roles through this system. Your current application remains active and will not be affected in any way.

Please note that we are currently not accepting applications from third party application services.