Principal Design Engineer, HBM Architecture

1000 Micron Technology, Inc.; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Micron Technology, Inc. is seeking a highly skilled HBM Datapath Engineer to architect, design, and optimize high-speed datapaths for next-generation HBM products in Richardson, Texas.

You will work across core and logic die to deliver robust datapath architectures with emphasis on bandwidth, power efficiency, and reliability. The role requires strong background in high-speed datapath design, RTL and schematic implementation, and collaboration with multiple engineering teams to bring designs

Qualifications

• 7+ years of relevant industry experience in high-speed datapath design.
• 3+ years of experience in high-speed digital datapath design (memory, SerDes, or SoC).
• 2+ years of hands-on RTL or mixed-signal datapath implementations.

Responsibilities

• Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic.
• Develop high-speed, low-latency datapath circuits for multi-channel HBM architectures.
• Collaborate with PHY, DFT, verification, and layout teams to ensure correct functionality and manufacturability.
• Drive RTL-level datapath implementations and validation across design reviews and documentation.

Skills

High-speed datapath design

RTL design

Schematic capture

Memory/DRAM architecture

Team collaboration

Education

Bachelor's in Electrical/Computer Engineering

Master's in Electrical Engineering

Job description

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The HBM Architecture team develops advanced datapath solutions that enable industry-leading bandwidth, power efficiency, reliability, and scalability for Micron's next-generation High Bandwidth Memory (HBM) products. The team collaborates closely across design, PHY, ECC, verification, layout, and system groups to drive innovative logic-die and core-die architectures from concept through production. We are seeking a highly motivated HBM Datapath Engineer to architect, design, and optimize high-speed data paths for next-generation High Bandwidth Memory (HBM) products! This role focuses on logic-die and core-die datapath circuitry, enabling industry-leading bandwidth, power efficiency, reliability, and scalability across JEDEC and custom HBM solutions. The ideal candidate will work closely with design, PHY, ECC, verification, layout, and system teams to deliver robust datapath designs from concept through silicon bring-up and production.

Responsibilities

• Architect and design HBM read and write datapath across core and logic die, including alignment, buffering, timing, and control logic
• Develop high-speed, low-latency datapath circuits supporting multi-channel HBM architectures and wide internal buses
• Optimize datapath designs for bandwidth, power, area, and timing closure at advanced technology nodes
• Design and integrate data reliability features, including parity, ECC hooks, lane redundancy, and remapping mechanisms
• Collaborate with multi-functional teams to translate specifications into robust micro-architectures
• Collaborate with PHY, DFT, verification, and layout teams to ensure accurate functionality, testability, and manufacturability
• Drive schematic-level and RTL-level datapath implementations, including clocking, gating, and reset strategies
• Contribute to design reviews, documentation, and technical mentoring across HBM programs
• Leveraging AI tools to efficiently carry out regular work

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field with 7+ years of relevant industry experience, or a Master’s degree with 5+ years of relevant industry experience.
• 3+ years of experience in high-speed digital datapath design (memory, SerDes, or SoC datapath).
• 2+ years of hands-on experience with digital schematic build, RTL, or mixed-signal datapath implementations.

Preferred Qualifications

• Strong understanding of HBM/DRAM architectures, including read/write data flow, timing, and multi-channel operation.
• Working knowledge of layout and floorplanning considerations for high-speed datapath.
• Experience with static timing analysis (STA) and timing-closure methodologies.
• Familiarity with advanced process-node challenges related to signal integrity, skew control, and power optimization.

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.

Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.

Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.

AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.

Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.