Power Integrity Engineer

Doist; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Medical, dental, and vision packages}

$500 monthly credit for waiving med

Housing subsidy for Santana Row living

Relocation support to San Jose

Wellness benefits

Daily lunch and dinner

Unlimited compute budget

Job summary

Etched is seeking a Power Integrity Engineer to own the PI methodology for high-current PCB and system designs, ensuring robust power delivery for ASICs and related components.

You will perform PDN analysis, VRM model development, and impedance/plane optimization while collaborating with power, PCB, and ASIC teams throughout the product lifecycle.

Qualifications

• B.S. or M.S. in Electrical Engineering or closely related discipline.
• 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery).
• Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent).
• Strong understanding of target impedance, decoupling networks, plane resonances, and anti-resonance mitigation.
• Experience with DC IR-drop analysis, current density limits, via/plane current-carrying capacity.
• Knowledge of VRM fundamentals: buck operation, multiphase design, transient response, load-line/AVP concepts.
• Knowledge of multi-layer PCB stack-up and power plane allocation strategies.

Responsibilities

• Own the power integrity methodology for high-power PCB and system designs from architecture through release.
• Perform pre- and post-layout PDN analysis and optimize decoupling, plane shapes, and via stitching.
• Develop and validate VRM models; analyze load transient response and AVP behavior.
• Collaborate with power design, PCB layout, and ASIC teams to review guidelines early in the product lifecycle.
• Support bring-up and diagnose rail-level issues with root-cause actions.

Skills

High-current PI design

Target impedance methodology

DC IR-drop analysis

VRM fundamentals

Multilayer PCB stack-up

Planar/via current-carrying capacity

Education

Electrical Engineering degree (B.S./M.S.)

Tools

Ansys SIwave

Cadence Sigrity PowerDC/PowerSI/OptimizePI

Equivalent PI EDA tools

Job description

# Power Integrity EngineerEtched • • • 5h agoSave this role or tell us whether you want more jobs like it.**About Etched**Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on **inference**. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.**Job Summary**We are looking for a Power Integrity (PI) Engineer to join our platform electrical engineering team. In this role, you will own the power integrity methodology for high-power PCB and system designs — from early architecture through final release — ensuring robust power delivery to high-performance ASICs and supporting components across all operating conditions.**Key Responsibilities*** Perform pre- and post-layout PDN analysis for high-current ASIC power rails: target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis.* Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers.* Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.* Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications.* Perform power-plane thermal co-simulation and work with mechanical teams on thermal-electrical tradeoffs for high-current delivery.* Drive design rule checks for PI compliance; work with layout teams in Cadence Allegro / Sigrity PowerDC/PowerSI or Ansys SIwave.* Collaborate with power design, PCB layout, and ASIC/package teams to define power delivery architecture and review guidelines early in the product lifecycle.* Support bring-up, debug rail-level issues (droop, ripple, transient excursions), and document root-cause findings with clear corrective actions.* Develop and maintain simulation-to-hardware correlation databases to continuously improve PDN modeling accuracy.**You may be a good fit if you have (Must-have qualifications)*** B.S. or M.S. in Electrical Engineering or a closely related discipline.* 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms).* Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent).* Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.* Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.* Working knowledge of VRM fundamentals: buck converter operation, multiphase design, transient response, and load-line/AVP concepts.* Working knowledge of multi-layer PCB stack-up design and power plane allocation strategies.**Strong candidates may also have experience with (Nice-to-have qualifications)*** Prior work in data center, AI/ML accelerator, networking, or high-performance computing (HPC) hardware environments.* Experience with vertical power delivery, high-current lateral delivery tradeoffs, or 48V-to-point-of-load architectures.* Package-level PDN co-analysis and experience working with die/package power models from ASIC teams.* Experience scripting automated PI simulation flows using Python or MATLAB to reduce manual simulation turnaround time.**Benefits*** Medical, dental, and vision packages with generous premium coverage + $500 per month credit for waiving medical benefits* Housing subsidy of $2k per month for those living within walking distance of the office* Relocation support for those moving to San Jose (Santana Row)* Various wellness benefits covering fitness, mental health, and more* Daily lunch and dinner in our office* Unlimited compute budget subject to ROI justification**How we’re different**Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.