Power Delivery and Power Integrity Architect

Qualcomm; Santa Clara (CA); On-site; USD 180,500 - 270,700; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced Power Delivery and Power Integrity Architect to define and verify end‑to‑end PDN solutions for data-center platforms.

You will collaborate with SoC, firmware, memory vendors, packaging, and platform teams to drive VR implementations and PDN modeling from die to system. The role requires strong PI fundamentals, multi‑phase VR design, and hands‑on experience with PI tools.

Qualifications

• Master’s degree in Electrical Engineering or related field; experience in Power Delivery preferred.
• 8+ years of experience in Power Delivery, board‑level VR design, PI analysis, simulation, and PDN measurements.
• Strong understanding of PI fundamentals, power supply architectures, voltage regulator technologies, chip supply design, and PDNs.
• Experience developing PI methodologies and PDN modeling from die to system, with model correlation and lab validation.
• Experience with server, HPC, or data center platform power delivery preferred.
• Experience with multi‑phase VR design/selection.
• Proficiency in PI simulation tools (e.g., Simplis/Simetrix, ADS, ANSYS SIwave, HFSS, and Cadence Sigrity PowerDC/PowerSI).
• Hands‑on experience creating complex PI models and simulations.
• Proficiency with Unix/Linux environments and EDA tools using scripting.

Responsibilities

• Collaborate with SoC, firmware/software, memory vendors, component suppliers, packaging, platform engineering, and system design teams to define and implement power architectures that meet internal and customer requirements.
• Lead voltage regulator (VR) design specification, selection, and co‑development with VR suppliers.
• Develop E2E VR + PDN simulation flows to reduce time to market.
• Perform PDN modeling, simulation, and characterization for SoC, package, PCB, VRs, and LDOs.
• Provide PI‑driven feedback to SoC design teams to influence decap, package, and power rail architecture.
• Create power maps, power tree and power‑flow diagrams, and power budgets from die to system level.
• Develop and provide implementation and system efficiency guidelines.
• Conduct IR drop, AC, and transient simulations and provide model‑to‑hardware correlations.
• Define module interfaces and formats for simulation and customer guidelines.
• Lead PI model creation, end‑to‑end PI simulations (thermal‑aware), and final design development considering heat sink and temperature effects.
• Leverage ML/AI‑assisted simulation techniques to streamline and automate design and analysis workflows from die to regulators.
• Prepare and present technical documentation and reports to stakeholders, including engineering teams, senior management, customers, and suppliers.
• Engage with customers and OEM partners to provide power delivery architecture guidance, PDN design guidelines, and bring‑up support.
• Troubleshoot system performance and identify areas for improvement.

Skills

Power Delivery

Power Integrity

VR design

PI simulation tools

Unix/Linux scripting

EDA tools scripting

Education

Master’s degree in Electrical Engineering or related field

Ph.D. in Electrical or Computer Engineering (preferred)

Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field

Tools

Simplis/Simetrix

ADS

ANSYS SIwave

HFSS

Cadence Sigrity PowerDC/PowerSI

Job description

Qualcomm Technologies, Inc.

Job Area: Engineering Group, Engineering Group > Systems Engineering

General Summary

Qualcomm Data Center team is developing high‑performance, energy‑efficient server solutions for data center applications. The team focuses on creating reference platforms based on Qualcomm’s Snapdragon SoC, delivering comprehensive solutions that include hardware, software, reference designs, user guides, SDKs, and more.

Position: Power Delivery and Power Integrity Architect

As an experienced Power Delivery and Power Integrity Architect (individual contributor), you will work closely with the platform team and cross‑functional teams—including software, firmware, circuit design, packaging, platform engineering, memory vendors, product management, and component suppliers—to define, analyze, simulate, and verify end‑to‑end power delivery and power integrity solutions from die to system level.

Key Responsibilities

• Collaborate with SoC, firmware/software, memory vendors, component suppliers, packaging, platform engineering, and system design teams to define and implement power architectures that meet internal and customer requirements.
• Lead voltage regulator (VR) design specification, selection, and co‑development with VR suppliers.
• Develop E2E VR + PDN simulation flows to reduce time to market.
• Perform PDN modeling, simulation, and characterization for SoC, package, PCB, VRs, and LDOs.
• Provide PI‑driven feedback to SoC design teams to influence decap, package, and power rail architecture.
• Create power maps, power tree and power‑flow diagrams, and power budgets from die to system level.
• Develop and provide implementation and system efficiency guidelines.
• Conduct IR drop, AC, and transient simulations and provide model‑to‑hardware correlations.
• Define module interfaces and formats for simulation and customer guidelines.
• Lead PI model creation, end‑to‑end PI simulations (thermal‑aware), and final design development considering heat sink and temperature effects.
• Leverage ML/AI‑assisted simulation techniques to streamline and automate design and analysis workflows from die to regulators.
• Prepare and present technical documentation and reports to stakeholders, including engineering teams, senior management, customers, and suppliers.
• Engage with customers and OEM partners to provide power delivery architecture guidance, PDN design guidelines, and bring‑up support.
• Troubleshoot system performance and identify areas for improvement.

Qualifications

• Master’s degree in Electrical Engineering or related field; experience in Power Delivery preferred.
• Strong experience in Power Integrity (PI).
• 8+ years of experience in Power Delivery, board‑level VR design, PI analysis, simulation, and PDN measurements.
• Strong understanding of PI fundamentals, power supply architectures, voltage regulator technologies, chip supply design, and PDNs.
• Experience developing PI methodologies and PDN modeling from die to system, with model correlation and lab validation.
• Experience with server, HPC, or data center platform power delivery preferred.
• Experience with multi‑phase VR design/selection.
• Proficiency in PI simulation tools (e.g., Simplis/Simetrix, ADS, ANSYS SIwave, HFSS, and Cadence Sigrity PowerDC/PowerSI).
• Hands‑on experience creating complex PI models and simulations.
• Proficiency with Unix/Linux environments and EDA tools using scripting.
• Knowledge of packaging and PCB technologies, design, and manufacturing processes.
• Knowledge of resonances, droops, IR drop, cooling, temperature effects, and power consumption.
• Familiarity with 2.5D/3D packaging technologies, including CoWoS, InFo, EMIB, and RDL.
• Strong experience in VR lab validation.
• Experience with electrical validation and compliance testing tools (VNAs, oscilloscopes, spectrum analyzers, TDR, differential probes).
• Proven ability to work independently and collaboratively within a cross‑functional team environment.
• Strong technical documentation skills and excellent written and verbal communication.

Preferred Qualifications

• Ph.D. in Electrical or Computer Engineering, specializing in Power Delivery.
• 10+ years of experience in Power Conversion, PI analysis, simulation, and PDN measurements.
• Experience with AI/ML‑accelerated computing platforms and their unique power delivery challenges.
• Strong knowledge of voltage regulator (VR) design principles and system‑level performance.
• Familiarity with open compute / hyperscale server reference designs.
• Expertise in PDN related EM analysis.
• Experience with package and PCB design tools (e.g., Cadence Allegro, Sip).
• Proficiency in scripting languages (MATLAB, Perl, Python).

Minimum Qualifications

• Bachelor’s degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.
• Master’s degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.
• Ph.D. in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

EEO Statement

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll‑free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Compensation & Benefits

Pay range: $180,500.00 - $270,700.00. This is the broad, minimum to maximum pay scale for the job code and location. Additional benefits include a competitive annual discretionary bonus program, RSU grants, and a highly competitive benefits package to support your success at work, at home, and at play.

Contact

If you would like more information about this role, please contact Qualcomm Careers.