Post-Silicon Server CPU Validation Architect

AMD; Austin (TX); Hybrid; USD 160,000 - 210,000; Full time

Benefits offered by this job

Hybrid work model

AMD benefits at a glance

Job summary

AMD seeks a Fellow, Post‑Silicon Validation Architecture for Server CPUs in Austin, TX. You will lead validation strategy, own test plans, and drive automation to ensure silicon quality from pre‑ to post‑silicon while collaborating with design, platform software, and hardware teams.

The role demands deep CPU architecture knowledge, executive‑level communication, and a track record of zero customer escape, enabling robust, scalable validation infrastructure for next‑generation server technologies.

Qualifications

• In-depth understanding of server CPU architecture and validation methodologies.
• Experience developing validation infrastructure and test plans.
• Strong English communication and executive-level presentation skills.

Responsibilities

• Drive the development of CPU validation strategy and test plan.
• Validation coverage & content/framework developer – owner of test strategy and execution to consistently find hard to detect CPU/SoC issues.
• Engage with technical leaders to develop tools and methodologies for validating next-generation server CPU technologies.
• At-scale validation strategist – direct the usage of global server farms to maximize quality.
• System level emulation architect – priority setter for emulation and prototyping.
• Drive automation capabilities for platform validation leading to product launch.

Skills

Executive communication

Analytical thinking

Debugging

Cross-functional collaboration

AI tools

Education

BSEE

MSEE preferred

Tools

C/C++

Python

Emulation tools

Job description

AMD seeks a Fellow, Post‑Silicon Validation Architecture for Server CPUs in Austin, TX. You will lead validation strategy, own test plans, and drive automation to ensure silicon quality from pre‑ to post‑silicon while collaborating with design, platform software, and hardware teams.

The role demands deep CPU architecture knowledge, executive‑level communication, and a track record of zero customer escape, enabling robust, scalable validation infrastructure for next‑generation server technologies.