Design Verification Engineer

Intel Corporation; Santa Clara (CA); Hybrid; USD 142,000 - 200,000; Full time

Job summary

Intel Corporation in Santa Clara, California, is seeking a Design Verification Engineer to verify interconnect and chassis IPs across product families. You will develop verification plans, build reusable environments, and drive first-pass silicon success with strong DV practices.

The role requires hands-on verification development using SystemVerilog, C/C++, Python, and AI-assisted tooling. The position offers a hybrid work model with collaboration across architecture, design, and software teams.

Qualifications

• BS/MS in Electrical Engineering, Computer Science, or related field; 3+ years in design verification
• Hands-on coding in SystemVerilog, C/C++, Python
• Foundation in simulation-based verification: UVM/ABV; testbench development, debugging, coverage-driven verification
• Hands-on experience with AI-assisted development tools for coding, debugging, and test development

Responsibilities

• Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level
• Build reusable verification components, checkers, constrained-random tests, and debug infrastructure
• Collaborate with architecture, design, and software teams on specs, bug triage, and closure
• Analyze simulation failures and drive fixes to closure with clear technical communication
• Contribute to functional coverage planning and coverage closure under guidance
• Improve verification automation, regression quality, and development efficiency

Skills

SystemVerilog

C/C++

Python

Education

BS/MS in Electrical Engineering or Computer Science

Tools

UVM/ABV

JasperGold

VC Formal

AI-assisted tools

Job description

Job Details:

Job Description:

Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will contribute to verification of next-generation interconnect and chassis IPs that scale across multiple product families. You will work closely with senior engineers to build and execute robust verification plans, develop high-quality reusable environments, and help deliver first-pass silicon success through strong design verification practices. This role requires strong programming and algorithmic problem-solving skills, hands-on verification development, and willingness to work across traditional discipline boundaries. AI-assisted workflows are part of everyday development here.

Responsibilities

• Develop and execute verification plans and testbenches for interconnect and chassis IP/features at IP and subsystem level
• Build reusable verification components, checkers, constrained-random tests, and debug infrastructure to improve coverage and productivity
• Work with architecture, design, and software teams on spec reviews, feature clarification, bug triage, and closure; contribute outside strict DV boundaries when needed
• Analyze simulation failures, root-cause issues quickly, and drive fixes to closure with clear technical communication
• Contribute to functional coverage planning, coverage closure, and quality signoff under guidance of technical leads
• Contribute to both simulation and formal verification efforts; continuously improve verification automation, regression quality, and development efficiency

You should also demonstrate: Proven ability to write clean, reusable, and maintainable verification code and automation scripts, and to collaborate effectively across architecture, design, and software teams

Qualifications:

Minimum Qualifications

• BS/MS in Electrical Engineering, Computer Science, or related field, with 3+ years of relevant experience in design verification
• Programming fundamentals and algorithmic problem-solving skills, with demonstrated hands-on coding experience in SystemVerilog, C/C++, and Python
• Foundation in simulation-based verification methodologies UVM/ABV, with exposure to formal verification concepts; testbench development, debugging, and coverage-driven verification
• Hands-on experience using AI-assisted development tools as part of daily workflow for coding, debugging, and test development

Preferred Qualifications

• Exposure to interconnects and bus protocols for example AMBA AXI/ACE/CHI, PCIe, CXL, UCIe
• Understanding of cache coherency and memory consistency models
• Experience with external interfaces and system integration debug
• Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification
• Exposure to RTL concepts, physical design, or CAD tool flows
• Prior work with system IPs such as MMUs SMMU or IOMMU and interrupt controllers

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Santa Clara

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel’s data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel’s product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USD

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.