Physical Design Sign-off Engineer

Apple Inc.; Austin, Northern (TX, KY); On-site; USD 150,000 - 230,000; Full time

Job summary

Apple Inc. in Austin, Texas seeks a Senior CAD Engineer to develop full-stack web applications powering the Signoff infrastructure across Apple SOC design groups.

Signoff is the critical final verification stage in chip design where designs are validated against manufacturing, timing, and power criteria before tapeout. You will build dashboards, CAD flow metrics collection, and data visualization tools that design and CAD teams rely on daily.

Qualifications

• BS in Computer Science or related field required.
• 10+ years of relevant industry experience.
• Proficient in Python, Perl or Tcl.
• Hands-on experience with industry PNR and timing tools (Cadence Innovus, ICC2/Fusion Compiler, PrimeTime, Tempus).
• Experience delivering designs through physical implementation and signoff.

Responsibilities

• Develop full-stack web applications powering the Signoff infrastructure.
• Build dashboards and collect CAD flow metrics for daily use by design/CAD teams.
• Create data visualization tools used by signoff teams.
• Contribute to Signoff AI assistant and integrate AI/RAG capabilities into the platform.

Skills

Python

Perl

Tcl

Education

BS in Computer Science or related field

Tools

Cadence Innovus

Synopsys ICC2 / Fusion Compiler

PrimeTime

Tempus

Kubernetes

Prometheus/Grafana

Job description

We're seeking a CAD Engineer to join our team and develop full-stack web applications that power the Signoff infrastructure across all Apple SOC design groups within the Hardware Tech group. Signoff is the critical final verification stage in chip design where designs are validated against manufacturing, timing, and power criteria before tapeout. This role focuses on building and enhancing Signoff dashboards, CAD flow metrics collection, and data visualization tools that design and CAD teams rely on daily. You'll also participate in the development of our Signoff AI assistant and integrate modern AI/RAG capabilities into our platform.

Minimum Qualifications

• BS in Computer Science or related field with 10+ years of relevant industry experience
• Proficient in programming using Python, Perl or Tcl
• Hands-on experience with industry PNR and timing tools such as Cadence Innovus, Synopsys ICC2 / Fusion Compiler, PrimeTime, or Tempus
• Experience taking block-level or chip-level designs through physical implementation and signoff closure on production silicon
• Experience in timing closure, signal integrity, low-power design techniques, and clock-tree construction
• Excellent communication skills and ability to collaborate across design, CAD, and technology teams
• Understanding of tradeoffs to meet PPA (power, performance, area) targets, and experience defining implementation recipes to improve PPA

Preferred Qualifications

• Background in Chip Design, Chip Verification, or CAD
• Experience with embedding models and LLM integration patterns
• Understanding of RAG pipelines, including embeddings, chunking, and retrieval optimization
• Experience with vector databases
• Experience with containers and Kubernetes
• Experience with monitoring and observability tools (Prometheus, Grafana)

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.