Physical Design Lead Engineer

Cisco Systems, Inc.; California, San Jose (MO, CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Join a forward-thinking company at the forefront of technology, shaping the future of connectivity. As a Technical Leader, you'll oversee the design and verification of cutting-edge ASICs, working with cross-functional teams to tackle complex challenges. This role offers the opportunity to mentor engineers and innovate within a dynamic environment. With a commitment to inclusivity and community engagement, this organization empowers its employees to thrive and make a difference. Embrace your potential and contribute to groundbreaking solutions that power the internet and transform industries.

Benefits

Dedicated paid time off to volunteer

Hybrid work environment

Employee resource organizations

Learning and development opportunities

Qualifications

• 10+ years of experience in ASIC implementation and physical verification.
• Strong knowledge of deep submicron CMOS technologies and physical design tools.

Responsibilities

• Oversee design and verification of ASICs, ensuring performance and compliance.
• Lead chip-level PNR activities and guide physical design engineers.

Skills

ASIC Implementation

Physical Verification

TCL Scripting

Perl Scripting

Deep Submicron CMOS Technologies

Education

BS in Electrical Engineering

MS in Computer Science

Tools

Cadence

Innovus

Synopsys IC Compiler

Fusion Compiler

Job description

Application Window Expected to close 05/10/25.

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.

Your Impact

As a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet performance, power, and area specifications. This role involves coordinating cross-functional teams, guiding design methodologies, and addressing technical challenges throughout the development process to ensure successful tape-out and compliance with industry standards. Responsibilities include:

• Lead chip-level PNR activities, from floor planning, bump and rdl planning, power grid design to clock planning, routing, and timing closure.
• Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results.
• Work closely with block and TOP level physical implementation, IP development teams and to resolve PV issues and address to proper owners.
• Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification robustness.
• Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with frontend, integration, and verification teams.

Minimum Qualifications:

• BS/MS in Electrical Engineering or Computer Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification
• Experience in deep submicron CMOS technologies.
• Experience with physical verification (DRC, LVS, ERC, ANT), debug, and solution.
• Scripting experience in TCL, Perl, or Makefile to streamline and automate workflows.
• Experience working with one or more of the following physical design tools, such as Cadence, Innovus, Synopsys IC Compiler, or Fusion Compiler.

Preferred Qualifications:

• Extensive experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support.
• Experience on 5nm nodes and below.
• Experience working with semiconductor foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams.
• Experience working with Package and floorplan teams to define padring and bump-map design.

WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!