Physical Design Engineer (VLSI Design) - Mountain View, CA (Hybrid) - Fulltime

ZipRecruiter; Mountain View (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

An established industry player is seeking a talented Physical Design Engineer specializing in VLSI Design. This full-time role in Mountain View offers a unique opportunity to engage in the backend VLSI design flow, focusing on critical tasks such as floor planning, placement, and timing closure. The ideal candidate will have extensive experience in Place and Route (PnR), Static Timing Analysis (STA), and EDA tools, contributing to innovative projects that push the boundaries of technology. Join a dynamic team and take your career to the next level in a hybrid work environment that fosters creativity and collaboration.

Qualifications

• 8-10 years of Physical Design experience in VLSI.
• Expertise in backend VLSI design flow and EDA tools.

Responsibilities

• Manage backend VLSI design flow including floor planning and timing closure.
• Perform standard cell placement and optimize for area and power.

Skills

Place and Route (PnR)

Static Timing Analysis (STA)

Synthesis

EDA Tools

Power Optimization

Performance Tuning

Scripting

Job description

Job Description

Our client is looking for a Physical Design Engineer (VLSI Design) for a full-time project in Mountain View, CA (Hybrid). Below are the detailed requirements.

Position: Physical Design Engineer (VLSI Design)

Location: Mountain View, CA (Hybrid)

Mode of hire: Full-time

Job Description:

Summary:

We seek a highly skilled Physical Design Engineer with experience in Physical Design, specializing in Place and Route (PnR) and Static Timing Analysis (STA). The role involves managing various aspects of the backend VLSI design flow, including floor planning, placement, clock tree synthesis (CTS), routing, timing closure, and sign-off verification. Expertise in EDA tools, physical verification methodologies, power optimization, and performance tuning is required.

Top 3 Skills: PnR, STA, and Synthesis with 8-10 years of Physical Design experience.

Responsibilities:

Block-Level Physical Design:

• Floor planning & Partitioning: Define optimal floorplan with power grid, macro placements, and congestion analysis.
• Strong scripting experience.
• Placement & Optimization: Perform standard cell placement, legalization, and optimization to improve area, power, and timing.
• Clock Tree Synthesis (CTS): Design and optimize low-skew, high-performance clock networks.
• Routing & DRC Closure: Ensure successful global and detailed routing, meeting design rule constraints.
• Timing Closure: Work on setup/hold timing violations, signal integrity, and cross-talk reduction using STA.
• Power & IR Drop Analysis: Optimize power planning, power integrity (IR drop, EM), and leakage reduction techniques.

Top-Level Physical Design:

• Chip-Level Floor planning & Hierarchical Design: Manage top-level layout planning, pin assignments, and cross-block optimizations.
• Strong scripting experience.
• Clock & Power Distribution: Design robust clock trees and power delivery networks (PDN).
• Integration of IP & Sub-blocks: Ensure seamless integration of IP blocks and handle complex routing challenges.
• Chip Assembly & Sign-Off: Perform final netlist-to-GDSII implementation, addressing physical and electrical verification.

DFT Integration:

• Work with Design for Test (DFT) teams to ensure scan chain connectivity and testability.