Physical Design Engineer (Silicon Engineering)

SpaceX; Austin (TX); On-site; USD 90,000 - 150,000; Full time

Job summary

SpaceX is seeking a Physical Design Engineer (Silicon Engineering) to develop next‑gen ASICs for Starlink satellites and ground systems. You will implement RTL‑to‑GDSII flows, optimize timing, power and area, and drive signoff readiness for space environments.

Bachelor’s degree in EE/CE/CS and 1+ years in RTL2GDSII physical design are required, along with familiarity with industry EDA tools and CMOS physics. SpaceX offers impactful projects, a collaborative culture, and growth opportunities.

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science.
• 1+ years of professional experience in RTL2GDSII physical design and/or physical design flow development.
• Experience with industry standard EDA tools and flow development.
• Understanding of CMOS deep sub‑micron physics and standard cells.

Responsibilities

• Perform partition synthesis and physical implementation steps including synthesis, floorplanning, P/G grid, place and route, timing, noise.
• Develop/improve physical design methodologies and automation scripts.
• Collaborate with the ASIC design team to drive feasibility studies and design targets, and explore RTL/design tradeoffs.
• Resolve design/timing/congestion issues and drive execution.
• Run signoff verification in STA, noise, and physical verification and fix issues.

Skills

RTL2GDSII flow

EDA tools

FinFET CMOS physics

CMOS digital design

CMOS power dissipation

DFT/MBIST/LBIST

Python scripting

Self-driven

Education

Bachelor's degree in Electrical/Computer Engineering or Computer Science

Tools

EDA tool suites

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best‑in‑class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world‑class cross‑disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting‑edge next‑generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting‑edge solutions that will expand the performance and capabilities of the Starlink network.

Responsibilities

• Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
• Develop/improve physical design methodologies and automation scripts for various implementation steps
• Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
• Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
• Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Basic Qualifications

• Bachelor’s degree in electrical engineering, computer engineering or computer science
• 1+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

Preferred Skills And Experience

• Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
• Knowledge of deep sub‑micron FinFET and CMOS solid state physics
• Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
• Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
• Familiar with CMOS analog circuit and physical design
• Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
• Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
• Self‑driven individual with a can‑do attitude, willing to learn, and an ability to work in a dynamic group environment

Additional Requirements

• Ability to work extended hours and weekends as needed to meet critical project milestones

Itar Requirements

• To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. 1157, or (iv) Asylee under 8 U.S.C. 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s affirmative action plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to [e-mail].